I hate VHDL!!!

[roller]

'if..elsif..elseif..endif' generates following equation:
A1.B1 + !A1.A2.B2 + !A1.!A2.A3.B3

If A1, A2 and A3 are mutually exclusive, and my suggestion is used:
'if..ORIF..ORIF..endif'
you will get the equation:
A1.B1 + A2.B2 + A3.B3
Same equation as if a "case" statement were used.

1. You tell compiler to generate statements like "case" statement.

so, again you admit that it'd be the same than a case statement....as you
previously admitted that there was no logic change while another poster
showed that indeed there was a possible optimization (something like the
solution i gave in the first place)

2. More items means long route, longer delay and decreased running
frequency.

The speed-up and resource saving is the FPGA chip final result, not
simulation!
I have never mentioned simulation saving.

When you don't fully understand a situation, you may feel it
"dangerous", "can of worm", "Pandora's box". But when you understand
it, it will makes your chip run faster and with confidence and without
any new simulation burden if and only if VHDL provides a means to do
that!

A CONCLUSION OF MUTUALLY EXCLUSIVE CONDITIONS IS NOT BASED ON THEIR
CONDITION VALUES, BUT ON PHYSICAL CONDITIONS!!!

no need to shout...

You are sleeping, you cannot be eating. And you are eating, you cannot
be sleeping;
You are at home, you cannot be at theater, you are at theater, you
cannot be at home;
You are dead, you cannot be alive, you are alive, you cannot be dead;
You are 20 years old, you cannot be 40 years old, you are 40 years
old, you cannot be 20 years old;
A true $20 note cannot be false, a false $20 note cannot be true;

But "You are a son, you cannot be a father, you are a father, you
cannot be a son" is wrong!!! You don't have to do simulations, no, not
a second, to prove if they are mutually exclusive.

So there is no confusion at all and there is never a "rare" "critical"
boundary condition to be tested!!!

If you can provide me with an example, I will tell you where you are
wrong.

no need, you didnt answer any of my previous questions on the
first place. And besides, i'll say it again, you ended up admitting that
your new keywords are identical to a "case", and also that there was no
logic
change.
In anycase, I agree with Tom (wallclimber)

 

[E. Timothy Uy]

Instead of the USPTO, you could just click here for the abstracts and
links to Espacenet:

http://patents.oncloud8.com/?pns=6,556,042;6,505,337;6,466,052;6,323,682;6,191,610;6,144,220

Tim
patents.oncloud8.com

 

[Weng Tianxiang]

1. What I said is if "orif"/"ofels"/"errels" are adapted as new key
words in VHDL, it can let users use it and "IT WILL GENERATE LOGIC SO
EFFICIENT AND FAST THAT IT IS SIMILAR TO CASE STATEMENT".

Do you know "case" statement is the most efficient and fastest
statement in VHDL?

2. "there was no logic change."
It means the following:
If you write statements:
if(A1) then
NextState <= S1;
elsif(A2) then
NextState <= S2;
elsif(A3) then
NextState <= S2;
end if;

then it can be changed in the following way to add mutually exclusive
conditions:
if(A1) then
NextState <= S1;
orif(A2) then
NextState <= S2;
orif(A3) then
NextState <= S2;
end if;

That's it. "NO OTHER LOGIC CHANGE" and it will give you saving!!!

Weng

 

[Just an Illusion]

Hi Tom ;-),

if (C1) then (E1) elsif (C2) then (E2) else (E3) =>
C1.E1+!C1.C2.E2+!C1.!C2.E3
if (C2) then (E2) elsif (C1) then (E1) else (E3) => C2.E2
+!C2.C1.E1+!C1.!C2.E3

I think that both equation aren't totally equivalent

JaI

 

[Just an Illusion]

Hi Weng,

1. What I said is if "orif"/"ofels"/"errels" are adapted as new key
words in VHDL, it can let users use it and "IT WILL GENERATE LOGIC SO
EFFICIENT AND FAST THAT IT IS SIMILAR TO CASE STATEMENT".

As roller previously said, your don't need to shout (uppercase words are
equivalent to shout in news group).

In summary, you propose to extend usage of 'case' keyword.

If you be able to use a mechanism of bit masking (or 'don't care') for
case with vector condition, you have your expected result.

Do you know "case" statement is the most efficient and fastest
statement in VHDL?

*joke* This is not the combinatory statement : s <=a and b; :0)

2. "there was no logic change."
It means the following:
If you write statements:
if(A1) then
NextState <= S1;
elsif(A2) then
NextState <= S2;
elsif(A3) then
NextState <= S2;
end if;

then it can be changed in the following way to add mutually exclusive
conditions:
if(A1) then
NextState <= S1;
orif(A2) then
NextState <= S2;
orif(A3) then
NextState <= S2;
end if;

That's it. "NO OTHER LOGIC CHANGE" and it will give you saving!!!

The real problem is that some mutually exclusive conditions come from
higher level that your entity/architecture block. If you want really a
reusable block, that is not pre-synthesized, you must let the full chip
synthesis decide how optimize your full design. In lot of case, some
local optimization can hardest the global optimization.

Weng

JaI

 

[Weng Tianxiang]

Sorry roller, but while I agree that adding these keywords is a bad

idea, it *is* true there are optimization benefits to it.

"bad idea?", why? for beginners? I just use 30% of VHDL structures and
never pay attention to what I have never used.

It is not a little benefit. My experiences told me that when I was
failing the final running frequency, either 66MHz for PCI or 133MHz
for PCI-X, the only way that helps me is to try to use more case
statements to reduce number of levels in "if..elsif..elsif..endif"
structure.

"if..elsif..elsif..endif" structure is Fortran language's product. In
software, there is no impact on performance, everything must be
executed in serial order. But in hardware, its essence is concurrent
implementation.

"if..orif..orif..endif" structure provides a similar, but excellent
structure to supplement "if..elsif..elsif..endif" structure: either in
serial implementation area or in concurrent implementation area.

Weng

 

[Just an Illusion]

Hi Weng,

...

"if..elsif..elsif..endif" structure is Fortran language's product. In
software, there is no impact on performance, everything must be
executed in serial order.

Do you know that the vhdl origin is ada, not fortran

But in hardware, its essence is concurrent implementation.

I am not agree with you about this point, 'case' is the concurrent
implementation 'spirit'; 'if' defined a policy of priority then you
expected than you found a mux cascade at the end.

"if..orif..orif..endif" structure provides a similar, but excellent
structure to supplement "if..elsif..elsif..endif" structure: either in
serial implementation area or in concurrent implementation area.

An other remark, you haven't any 'serial' implementation area, but
'sequential' ;-)

And neither 'if' nor 'case' can be define into a concurrent statement
area. They are typically sequential statement (must be embedded into a
process statement part, that is a sequential statement). It is not
because process executions are concurrent, than there 'code' is
concurrent too.

Weng

Rgrds,
JaI

 

[Weng Tianxiang]

I would like to show you with real code in my PCI-CORE why it is very
important to introduce "if..orif..endif" keywords into VHDL to clear
any confusions about mutual exclusive conditions.

This is very common equations in PCI core design.
A register of 5-bits at my PCI configuration space address 0x07 is
targeted by PCI host to write new data into it. When PCI bus is 32-bit
width, the write data is in low 32-bit PCI bus, if PCI bus is 64-bit
width, the write data is in high 32-bit PCI bus. There is another
internal clear signal to initialize the register.
if(DIMMNumberClear) then
DIMMNumber(4 downto 0) <= (others=>'0');

elsif(CSRAD_R0_L_DIMMNumber_H and nC_BE_R0(3 downto 0) = "0111") then
if(AD_R0(28) = '1) then
DIMMNumber(4 downto 0) <= "10000";
else
DIMMNumber(4 downto 0) <= AD_R0(28 downto 24);
end if;

elsif(CSRAD_R0_H_DIMMNumber_H and nC_BE_R0(7 downto 4) = "0111") then
if(AD_R0(60) = '1') then
DIMMNumber(4 downto 0) <= "10000";
else
DIMMNumber(4 downto 0) <= AD_R0(60 downto 56);
end if;
end if;

3 levels in the 'if..elsif..endif'.

First level has highest order to clear.

Second and 3rd are mutually exclusive.
Because PCI-bus is either 32-bit width or 64-bit width.
If you choose any other current legal writing to get its performance
benefit, you would destroy the simplicity of above equations, but if
you don't, you have to pay penalty to the priority tree inherited in
'if..elsif..endif'.

If "if..orif..endif" keywords is introduced into VHDL, how nice it
fits into the situations!

if(DIMMNumberClear) then
DIMMNumber(4 downto 0) <= (others=>'0');

elsif(CSRAD_R0_L_DIMMNumber_H and nC_BE_R0(3 downto 0) = "0111") then
if(AD_R0(28) = '1) then
DIMMNumber(4 downto 0) <= "10000";
else
DIMMNumber(4 downto 0) <= AD_R0(28 downto 24);
end if;

orif(CSRAD_R0_H_DIMMNumber_H and nC_BE_R0(7 downto 4) = "0111") then
if(AD_R0(60) = '1') then
DIMMNumber(4 downto 0) <= "10000";
else
DIMMNumber(4 downto 0) <= AD_R0(60 downto 56);
end if;
end if

1. Mutually exclusive case is easy to recognize if you pay attention
to it;
2. No any "critical boundary" exist!
3. No any confusion about simulations!
4. Not danger at all!

Any comments special to the above example are welcome.

Weng

 

[Mike Treseler]

I would like to show you with real code in my PCI-CORE why it is very
important to introduce "if..orif..endif" keywords into VHDL to clear
any confusions about mutual exclusive conditions.

Any comments special to the above example are welcome.

see:
http://groups.google.com/groups?q=overlapping+cases+priority+hinze

-- Mike Treseler

 

[roller]

I would like to show you with real code in my PCI-CORE why it is very
important to introduce "if..orif..endif" keywords into VHDL to clear
any confusions about mutual exclusive conditions.

right, cause you're the only one who actually need it...

Any comments special to the above example are welcome.

Weng

yes, it's never late to learn...
i cant believe this issue is still being discussed while several solutions
were showed to be feasible...

 

[roller]

"bad idea?", why? for beginners? I just use 30% of VHDL structures and
never pay attention to what I have never used.

and maybe you should...because "case" didnt seem to fit in your 30%

It is not a little benefit. My experiences told me that when I was
failing the final running frequency, either 66MHz for PCI or 133MHz
for PCI-X, the only way that helps me is to try to use more case
statements to reduce number of levels in "if..elsif..elsif..endif"
structure.

"if..elsif..elsif..endif" structure is Fortran language's product.

man, VHDL comes from ADA...and the need for "if...endif" is to give
priority, whether Fortran, C and every other language uses it or not is not
the issue here.

In software, there is no impact on performance, everything must be
executed in serial order. But in hardware, its essence is concurrent
implementation.

and it was showed that could be achieved without new keywords...

"if..orif..orif..endif" structure provides a similar, but excellent
structure to supplement "if..elsif..elsif..endif" structure: either in
serial implementation area or in concurrent implementation area.

whatever man

 

[roller]

1. What I said is if "orif"/"ofels"/"errels" are adapted as new key
words in VHDL, it can let users use it and "IT WILL GENERATE LOGIC SO
EFFICIENT AND FAST THAT IT IS SIMILAR TO CASE STATEMENT".

Do you know "case" statement is the most efficient and fastest
statement in VHDL?

2. "there was no logic change."
It means the following:
If you write statements:
if(A1) then
NextState <= S1;
elsif(A2) then
NextState <= S2;
elsif(A3) then
NextState <= S2;
end if;

then it can be changed in the following way to add mutually exclusive
conditions:
if(A1) then
NextState <= S1;
orif(A2) then
NextState <= S2;
orif(A3) then
NextState <= S2;
end if;

That's it. "NO OTHER LOGIC CHANGE" and it will give you saving!!!

Weng

whatever you say dude