For instantiating both the RTL and the netlist in the same testbench,
I just renamed the entity of the netlist to procedureTest_syn, that
was a quick and dirty solution and not having to think about writing a
configuration ;-)
Note the happy coincidence
that both ise and quartus netlists
happen to name their architectures "structure".
So I can specify that directly for the i_SYN instance
and not modify the netlist entity or testbench
for either case.
I don't even have to write a component declaration
with direct instances like this:
i_DUT: entity work.proc_demo(rtl)
-- proc_demo.vhd architecture
port map (clk => clk, -- [in]
rst => rst, -- [in]
incr => incr, -- [in]
decr => decr, -- [in]
data => data); -- [out]
------------------------------------------------
i_SYN: entity work.proc_demo(structure)
-- both ise and quartus use this architecture
port map (clk => clk, -- [in]
rst => rst, -- [in]
incr => incr, -- [in]
decr => decr, -- [in]
data => data_syn); -- [out]
Your testbench worked brilliantly, by the way.
-- Mike Treseler