Random Number Generation in VHDL

[Ray Andraka]

Make a ring counter which nearly oscillates at 1/1024th (say) frequency as
your off-chip clock.

Divide the external clock by 1024, then compare and count the phase
difference in clock cycles.

Hey presto a random number ! (well nearly) which is different every time
you switch on.

You have to be careful using a ring oscillator on-chip, as chip
parasitics will cause it to sync up to other clocks on the chip, and you
will lose randomness. That said, as long as you use the ring oscillator
right at start-up before it has an opportunity to lock to the system
clock, you will probably be OK.

Alternatively, if you have two independent external clocks, you can use
a divided version of one to capture the state of a toggle flip-flop
clocked by the other (or a divided version of the other) to determine if
there are an even or odd number of clocks between successive edges.
Assuming the two clocks are truely asynchronous to one another, you will
get a good quality one bit random for each event. Use successive events
to assemble a parallel seed value (note for an LFSR you can just clock
the bits in as they occur, so there is no need to deserialize it.

Additionally, the LFSR only produces one new pseudo-random bit for each
clock, so if you need more than a 1 bit random, you need to operate the
LFSR for the number of clock cycles equal to number of bits you need.
Obviously, the LFSR has to have a long enough sequence so that only a
small fraction of the cycle is completed within your longest observation
window in order for the bits to appear random.

If your clocks really are de-correlated, then you don't need the LFSR at
all, you can just use the odd/even timing measurement of the successive
edges between the two clocks and get a good random.