M
Martin Thompson
rickman said:Are you saying that Emacs understands VHDL well enough to build a test
bench for you? Will it also build a component declaration or
instantiation automatically? These three things could be automated,
but I have never taken the time to do it. Making it part of the
editor makes perfect sense.
Here's an example:
Given this (for which I typed very few letters due to autocompletion
and other magic):
entity example is
generic (
blah : integer := 5);
port (
clk : in std_logic;
reset : in std_logic;
a : in integer;
b : out integer);
end entity example;
I can "copy-port" and "paste as testbench" to get this (I have done
nothing further to it at all):
< being vhdl paste >
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------------------------------------------------------------------
entity tb_example is
end entity tb_example;
----------------------------------------------------------------------------------------------------------------------------------
architecture test of tb_example is
-- component generics
constant blah : integer := 5;
-- component ports
signal clk : std_logic;
signal reset : std_logic;
signal a : integer;
signal b : integer;
-- clock
signal Clk : std_logic := '1';
-- finished?
signal finished : std_logic;
begin -- architecture test
-- component instantiation
DUT: entity work.example
generic map (
blah => blah)
port map (
clk => clk,
reset => reset,
a => a,
b => b);
-- clock generation
Clk <= not Clk after 10 ns when finished /= '1' else '0';
-- waveform generation
WaveGen_Proc: process
begin
finished <= '0';
-- insert signal assignments here
finished <= '1';
report (time'image(now) & " Finished");
wait;
end process WaveGen_Proc;
end architecture test;
----------------------------------------------------------------------------------------------------------------------------------
configuration tb_example_test_cfg of tb_example is
for test
end for;
end tb_example_test_cfg;
----------------------------------------------------------------------------------------------------------------------------------
< end vhdl paste >
I still need to update the vhdl-mode config so that clk doesn't get
defined twice - I broke that at some point, and haven't gone back to
fix it properly, I just delete the line. That feels very lazy, now
I'm admitting it
Cheers,
Martin