The littlest CPU

[rickman]

Which one is your CPU? Is it open source?

Mine was done some 6 or 7 years ago for a simple application and I
never released it. I have called it "Bonus" for no special reason.
If I decide to open source it I will try to come up with a better
name.

I don't know that it is anything special at this point. There are a
*huge* number of CPUs available at opencores.org and other places. A
quick count at opencores gives 93 processors, not counting the special
purpose ones! Does the world really need another one???

The only problem is that most of them are not really very well
documented. Very few of them even tell you how large they are in an
FPGA or how fast they run. Heck, there are three just called,
"Microprocessor" and one of those doesn't even have a page! We seem
to have quantity, but quality only in a few.

Rick

 

[rickman]

Yes, I like the idea of prefix instructions -- I am a believer in
compact instruction sets, even if it makes the CPU slightly more
complex. The transputer linker had the same issues you allude with
yours -- the linker would sometimes have to make many 10's, or even a
few hundred passes (for a large program) to make all of the variable
length prefix instructions as short as possible. That is probably one
of the reasons that the successor to the transputer fromwww.xmos.com
looks much more like a modern register-based architecture with a lot of
other clever transputer features retained or extended. Sauermann
started with the 8080/Z80 only to come across the poor match to a C
compiler. Since this was his starting point, I am not surprised that
his final design shows some heritage from these designs. I would be
very interested in knowing how your design fares with a C compiler (if
someone smarter than me has the strength to do the port).

I want to say the ZPU is a stack oriented processor, two stacks in
fact, like you would use for Forth; one is for data and the other for
addresses, but I don't recall and I can't seem to find the docs on my
hard drive. But ZPU has a C compiler, so you could compare this one
to other, non-stack processors.

Rick

 

[Colin Paul Gloster]

On Wed, 23 Jul 2008, Robert F. Jarnot wrote:

|-------------------------------------------------------------------------------|
|"[..] |
| |
|[..] The |
|transputer linker had the same issues you allude with yours -- the linker would|
|sometimes have to make many 10's, or even a few hundred passes (for a large |
|program) to make all of the variable length prefix instructions as short as |
|possible." |
|-------------------------------------------------------------------------------|

Yikes.

|-------------------------------------------------------------------------------|
|" That is probably one of the reasons that the successor to the |
|transputer from www.xmos.com looks much more like a modern register-based |
|architecture with a lot of other clever transputer features retained or |
|extended. [..]" |
|-------------------------------------------------------------------------------|

So do the linkers for XMOS devices use only a few passes?

Are radhard versions of XMOS devices available?

With best regards from Portugal,
Paul Colin

 

[Frank Buss]

I may need to add a CPU to a design I am doing. I had rolled my own
core once with a 16 bit data path and it worked out fairly well. But
it was 600 LUT/FFs and I would like to use something smaller if
possible.

I think an interesting architecture would be a Turing machine. It was
proved that a 7-state 4-symbol machine is an universal Turing machine (can
be reduced even more, if you figure out how to use Wolfram's rule 110,
which can be emulated by a smaller Turing machine, to implement arbitrary
computer programs). This means a lookup table of 28 entries, where each
entry is 6 bits, and an up-/down counter for accessing the memory,
organized in 2 bits words, is sufficient. I would use another BRAM for the
lookup table, then the number of LUTs should be very low to implement the
Turing machine.

Of course, the maschine would be unbelievable slow and would need some
major work to implement a GCC backend for it, but you could even implement
it with a fistful of standard logic ICs