entity Test2 is
Port ( Clk50 : in STD_LOGIC;
Reset : in STD_LOGIC;
DataReady : in STD_LOGIC;
B : in STD_LOGIC_VECTOR (23 downto 0);
Bup, Benable :out STD_LOGIC);
end Test2;
architecture Behavioral of Test2 is
type States is (Detect_Dataready0,Detect_Dataready1, Test_for_stable_B,
Test_B, Make_Bup_Puls);
signal State: States;
signal Counter: integer range 0 to 63;
signal NewB1,NewB2,Last_B: STD_LOGIC_VECTOR (23 downto 0);
signal Sync_B: STD_LOGIC_VECTOR (23 downto 0);
signal Sync_DataReady: STD_LOGIC;
constant Bmin: std_logic_vector (23 downto 0) := "000011001010101111110011";
constant Bmax: std_logic_vector (23 downto 0) := "000011011001110110010001";
begin
Syncronize: process( Clk50) -- THIS PROCESS TOO MAKE EVENTUALLY ASCYNCRONE SIGNALS- SYNCRONE WITH Clk50
begin
if Rising_edge(Clk50) then
Sync_B <= B;
Sync_DataReady <= DataReady;
end if;
end process Syncronize;
FSM: process( Clk50)
begin
if rising_edge( clk50) then
if Reset='1' then
State <= Detect_Dataready0;
Bup <= '0';
else
case State is
when Detect_Dataready0 =>
Benable <= '0';
Bup <= '0';
if Sync_Dataready='0' then
State <= Detect_Dataready1;
end if;
when Detect_Dataready1 =>
Benable <= '0';
Bup <= '0';
if Sync_Dataready='1' then
NewB1 <= Sync_B;
NewB2 <= NewB1;
State <= Test_For_Stable_B;
end if;
when Test_for_Stable_B =>
NewB1 <= Sync_B;
NewB2 <= NewB1;
if NewB1 = NewB2 then
State <= Test_B;
end if;
when Test_B =>
------------------------------------------------------
if ( NewB2 > Bmin and NewB2<Bmax ) then
Benable <= '1';
else
Benable <= '0';
end if;
-------------------------------------------------------
Bup <= '0';
if NewB2 > Last_B then
Counter <= 1;
State <= Make_Bup_Puls;
else
State <= Detect_Dataready0;
end if;
Last_B <= NewB2;
when Make_Bup_Puls =>
Counter <= Counter+1;
Bup <= '1';
if Counter > 49 then
State <= Detect_Dataready0;
end if;
end case;
end if;
end if;
end process FSM;
end Behavioral;
