Or, maybe stick with vhdl-make.
It can be worth the wait.
Hey....I thought earlier in the thread you implied (at least to me)
that this was lightning quick
If I forget about some package edit
I made at the beginning of my session,
'Compile out of date' may lead me
on a long debug session.
For what it's worth, I haven't found that to be the case. If
something changes inside a package/entity that will require a re-
compile of some dependent file that was not changed (and therefore not
caught by 'Compile out of date' then it gets flagged as soon as you
vsim. The message is pretty clear, telling you which design unit
needs to be recompiled because package 'xyz' has been changed.
The amount of lost time would be the time spent loading the design up
to the point of the failure (which I'm guessing for most would be less
than 1 minute), not any debug time (since you can't get that far). In
any case, you would recompile the dependent files and get back to
siming.
This is all on the assumption that the file dependencies have all been
worked out correctly to begin with....and if they haven't....well, the
GUI (and I'm guessing the command line too based on NigelE's earlier
post) does have a 'generate compile order' option as well. Whether
that is better or worse than what people use to generate file
dependency orders to feed into make is something for each to decide.
Kevin Jennings