(e-mail address removed) wrote:
> Sergey
>
> I see that you are using ieee.numeric_std in the same file, and I'm not
> sure if this is allowed. I think it introduces function/operator
> overloading, and in my experience there are vendor specific subtleties
> in how this is handled.
>
> Where Modelsim can happily resolve the difference between "+" based on
> whether the argument is "signed" or "sfixed," these are actually
> subtypes based on the same "array of std_ulogic" type. The standard
> doesn't allow resolution based on subtypes, so that might explain why
> ISE can't tell the difference. I stand to be corrected on this, perhaps
> one of the guru's can clarify.
>
> Anyway, try taking numeric_std out and see what happens.
>
> Richard
>
>
>
>
>
>
> Sergey Katsev wrote:
>> Here's the test file I'm using:
>>
>> library ieee;
>> library ieee_proposed;
>> use ieee.std_logic_1164.all;
>> use ieee.numeric_std.all;
>> use ieee_proposed.math_utility_pkg.all;
>> use ieee_proposed.fixed_pkg.all;
>> entity fixed_synth is
>>
>> port (
>> in1, in2 : in ufixed (4 downto -5); -- inputs
>> out1 : out ufixed (4 downto -5); -- output
>> clk, rst_n : in STD_ULOGIC); -- clk and reset
>>
>> end entity fixed_synth;
>>
>> architecture rtl of fixed_synth is
>> signal outarray : ufixed (4 downto -5);
>>
>> begin -- architecture rtl
>> -- purpose: "0010" test the "*" operator
>>
>> moo: process (clk)
>> begin
>> if (rising_edge(clk)) then
>> outarray <= resize(in1 / in2, 4, -5);
>> end if;
>> end process moo;
>>
>> out1 <= outarray;
>>
>>
>> end architecture rtl;
>>
>>
>> (e-mail address removed) wrote:
>>> Sergey
>>>
>>> OK, I presume you downloaded the latest version off the web. I just got
>>> it and tried to run it, and also got errors. I tihnk it might be in a
>>> state of flux right now. I'm using the previous version which you can
>>> get from
>>> http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/additions_16.tar.Z
>>>
>>> If you use it you don't need the utility package. Give it a try and see
>>> what happens. Also, to start with, maybe don't try and synthesize
>>> fixed_syth.vhd. Rather write your own vhdl file with a single entity
>>> that just does a single fixed point multiply. Then see if you can get
>>> that to work.
>>>
>>> Richard
>>>
>
I commented out numeric_std (it wasn't needed anyway), and the same
problem persists...
Any other ideas? Is there any hope of getting this to work in ISE?
-- Sergey
