VHDL language is out of date! Why? I will explain.

[Helmut]

I agree that VHDL has some disadvantages when I comes to syntax
features.But if there is not a synthesis tools, I just can´t use any
other language to program my FPGA.

 

[Mike Treseler]

I agree that VHDL has some disadvantages when I comes to syntax
features.But if there is not a synthesis tools, I just can´t use any
other language to program my FPGA.

Sorry. Let me fix that subject line.
I agree with you.
The thread went off on a tangent
as they often do

-- Mike Treseler

 

[Nico Coesel]

I think that there is something to be gained from using 'whatever', but it
depends - if you are full-time vhdler working on small or large FPGA
designs then fine; if you are an electronics engineer who on a reasonably
regular basis has an FPGA that needs to be designed/verified then vhdl is
(IMO of course) too complex, and, for test benches in particular, too
cumbersome.

In that perpective, using C would have made much more sense. Most
electronics engineers can write software in C. Having to use python is
like trading one obscure language for another.

Anyway, I've been using VHDL for a couple of years now (on and off)
and I must say it has its disadvantages, but it also is pretty
powerfull. I particulary like the functions and records. They allow me
to write complex stuff in just a few lines.

 

[Paul Taylor]

Interesting.
I now handle this manually by using annoying
identifiers for the unsynch nodes.
Maybe "run_glitchy" vs "run".


OK here's mine.
I get automated mistake-finding at the
editor, analysis, and elaboration level
of each library unit.

1. Emacs vhdl-mode completes keywords
and identifiers, matches most parens
and prompts for clauses in a keyword statement.
This prevents most syntax errors from happening.

2. I run simulation analysis
vcom -c mydesign.vhd
from an editor function key every few lines of code.
This step finds the most errors
but puts the cursor right on each one
and tells me what's wrong.

I would estimate:
90% syntax punctuation: missing or excess : ; ) etc.
10% static mismatch of code with local or library subtypes.
Length, range etc.
10% signature mismatch of code and local or library subprograms

At the top level, Emacs vhdl-make automatically finds
units with multiple declarations in the project path, like this:
WARNING: Architecture declared twice (used 1.): "synth" of "cnt_decode"
1. in "~/vhdl/play/cnt__decode.vhd" (line 18)
2. in "~/vhdl/play/cnt_decode.vhd" (line 18)

3. elaboration:
vsim -c mydesign
will find most runtime mismatches
and give a pretty good description of what's wrong.
Some messages are more cryptic hints at infinite loops,like
** Fatal: Write failure in vlm process (32,-1)

That leaves the functional errors to simulation
viewers and assertions, but I have no automated
method for this.

-- Mike Treseler

Thanks for info,

Paul.

 

[reiner]

See the extremely bad opinion of Joe Costello as former CEO of
CADENCE:
http://xputers.informatik.uni-kl.de/staff/hartenstein/karlHistory.html#Costello

Archimedes Neutrino

 

[Jan Decaluwe]

MyHDL is a one man show.

MyHDL is set up as a typical open-source project. It is as open as possible
and encourages people to contribute. People do contribute when it's useful
to them, and they do so for MyHDL. Of course, there is a benevolent dictator
(yours truly) to set the pace and to arbitrate.

So the statement above is disrespectful to all those who contributed in some
form to MyHDL. I immediately add that I'll take the blame: I haven't
acknowledged these contributions explicitly enough in the past. I'll try
to fix that, and I apologize to all those concerned.

> I doubt that Python is the ideal language based for
hardware description. I believe it is possible to design a very concise dynamic
language for hardware design. But this will significantly more than one person
to bring it up. My impression is MyHDL is not very suitable for large projects now.

doubt, believe, impression ... instead of spreading FUD, why not just
tell us about our complaints and the features you are missing. (Not in this
newsgroup of course.)

Jan

 

[Nico Coesel]

doubt, believe, impression ... instead of spreading FUD, why not just
tell us about our complaints and the features you are missing. (Not in this
newsgroup of course.)

Aside the obstacles I mentioned in my earlier post, I'm also concerned
about the ability of MyHDL to write clever code. I would like to know
how you can implement a 16 to 4 priority encoder in MyHDL....

 

[Jan Decaluwe]

Aside the obstacles I mentioned in my earlier post, I'm also concerned
about the ability of MyHDL to write clever code. I would like to know
how you can implement a 16 to 4 priority encoder in MyHDL....

Just like you would in VHDL or Verilog: loop over the input bits
and break out early as soon as a '1' is found.

No cleverness needed, just an HDL with support for procedural statements.

Jan

 

[bedrr]

really ?

so think about verilog !

 

[Wolfgang Grafen]

MyHDL is set up as a typical open-source project. It is as open as possible
and encourages people to contribute. People do contribute when it's useful
to them, and they do so for MyHDL. Of course, there is a benevolent
dictator
(yours truly) to set the pace and to arbitrate.

So the statement above is disrespectful to all those who contributed in
some
form to MyHDL. I immediately add that I'll take the blame: I haven't
acknowledged these contributions explicitly enough in the past. I'll try
to fix that, and I apologize to all those concerned

Whether it is disrespectful or not depends on the view point. For one
person or probably a hand full person it is a great effort. I didn't
mean it in a negative way.

doubt, believe, impression ... instead of spreading FUD, why not just
tell us about our complaints and the features you are missing. (Not in this
newsgroup of course.)

First of all, I miss sufficient documentation and really useful examples. A
large project I think of has some millions gate coded in hundreds of blocks
designed by five or more hardware designers with several clock domains
and will finally work. It should be able to efficiently simulate, write
back synthesis timing information and so on.

I like Python for a long time. Python was not designed for hardware
design. The ideal language has the most comprehensive syntax and good
support e.g. for parallel processes. It can be done in Python, but with
less comprehensive syntax and less simulation performance compared to an
optimised language.

Of course, this is only my opinion. I promise I will look over MyHDL
again (did it last half a year ago).

Best regards

Wolfgang

 

[psihodelia]

Mr. Decaluwe,

you do great work !
Do not listen any disrespectful troll who has no idea what is MyHDL.

What is still missed on MyHDL page are clear informative examples and
tutorials. Current domain name is also bad to remember. Menu structure
is also poor.

Thanks in advance!

 

[Mike Treseler]

What is still missed on MyHDL page are clear informative examples and
tutorials.

What's wrong with this one?
http://myhdl.jandecaluwe.com/doku.php/cookbook:sinecomp

-- Mike Treseler

 

[Jim Granville]

Mr. Decaluwe,

you do great work !
Do not listen any disrespectful troll who has no idea what is MyHDL.

What is still missed on MyHDL page are clear informative examples and
tutorials. Current domain name is also bad to remember. Menu structure
is also poor.

Thanks in advance!

You did see the examples here - maybe slighly miss-named as cookbook ?

http://myhdl.jandecaluwe.com/doku.php/cookbook:intro

Jan added fitter reports and mapping results to these examples, and
they are quite good.

-jg

 

[Jan Decaluwe]

First of all, I miss sufficient documentation and really useful examples. A
large project I think of has some millions gate coded in hundreds of blocks
designed by five or more hardware designers with several clock domains
and will finally work. It should be able to efficiently simulate, write
back synthesis timing information and so on.

I like Python for a long time. Python was not designed for hardware
design. The ideal language has the most comprehensive syntax and good
support e.g. for parallel processes. It can be done in Python, but with
less comprehensive syntax and less simulation performance compared to an
optimised language.

Of course, this is only my opinion. I promise I will look over MyHDL
again (did it last half a year ago).

My opinion is quite different but let's discuss this further in the
MyHDL newsgroup if you want to.

Anyway, this implies that MyHDL is likely to disappoint you. Also,
it will probably work better for "agile" hardware design based on
programmable platforms than for the mega-asic projects that
you are describing.

However, I believe those will become out of date long before VHDL does

Jan

 

[Wolfgang Grafen]

My opinion is quite different but let's discuss this further in the
MyHDL newsgroup if you want to.

No, MyHDL doesn't disappoint me. I will give it another try. I would
like to have something Pythonic like MyHDL in my work flow

> Also, it will probably work better for "agile" hardware design based on
> programmable platforms than for the mega-asic projects that
> you are describing.

The pressure to have a better HDL language is not as high as a better
language for verification. I could imagine MyHDL could excel here. AFAIK
you can use MyHDL through the Verilog external interface. When I tried
MyHDL last VHDL language generation support was just coming.

>
> Jan

Wolfgang

 

[Wolfgang Grafen]

You did see the examples here - maybe slighly miss-named as cookbook ?

http://myhdl.jandecaluwe.com/doku.php/cookbook:intro

Jan added fitter reports and mapping results to these examples, and
they are quite good.

-jg

Yes, I saw it and followed some examples before. Now I remember, I had
problems
describing and simulating a design composed of several modules. It is
only me - I didn't know how to do it and I would like the documentation
extended in this way. People who have to decide whether MyHDL will used
for a project or not would like to see even more, a proof, e.g. a
complete project, multiple clock domains, individual delays on signals
(after...ns), asynchronous logic handling come in my mind. The
developpers might know MyHDL can do all that, but naturally there is the
fear that approaching the top from the bottom a system might fail
somewhere inbetween.

MyHDLs documentation is becoming better and better. I honour that.

Just my 2 cents

Wolfgang

 

[psihodelia]

The Motto of MyHDL Project says: "From Python to silicon". Many people
are interested to see any clear example of how one can produce a bit
file for a FPGA from MyHDL.

For example, it could be an example of binding MyHDL with popular XST,
demonstrating, say, simple UART/VGA/LED/ or even SRAM controller. At
the same time, VHDL analogous program should be available for the
comparison.

In that case, people can compare two digital design flows, executed
using different languages. Results will show the quality of
synthesized code, expended translation/synthesis time, and maybe will
reveal some difficulties.

Of course, MyHDL has preliminary preference because of its simplicity,
syntax, and power.

 

[Mike Treseler]

The Motto of MyHDL Project says: "From Python to silicon". Many people
are interested to see any clear example of how one can produce a bit
file for a FPGA from MyHDL.

The open source motto says: "Try it and see."

For example, it could be an example of binding MyHDL with popular XST,
demonstrating, say, simple UART/VGA/LED/ or even SRAM controller.

That binding is verilog code.
Run it through your tools and see if works.

The process of converting verified hdl code
into an fpga image is vendor specific.
I would have as little interest in hearing
about the xst process as you would hearing
about quartus.

At the same time, VHDL analogous program should be available for the
comparison.

Open source projects have no marketing department.
Such comparisons are done by interested users.

-- Mike Treseler

 

[psihodelia]

Mike, you are great man,
you deserve respect for what you've done,
I grew up on your VHDL materials (and a lot of others as well),
but that's a hit at me;
why so sadistic irony ?

I am proponent of Open Source ideology, you know it, and
I do I believe that egoistic actions stops real progress in the
science, in the industry, in the society,
it stops to bring new knowledge to others.

To others, who has no gates to best universities. Don't ever forget
about that it's a lot of young people
sometimes maybe from the very edges of the world who has not enough
abilities to get knew knowledge.

But many have now the Internet. And they spent their money to study
new things,
they pay their last money only to have an access to WWW.

We are to help them, to share our knowledge.

An Open Source motto is not just "Try it and see." ,
it is much more to went into it full bore.

 

[Jan Decaluwe]

Now I remember, I had problems
describing and simulating a design composed of several modules. It is
only me - I didn't know how to do it and I would like the documentation
extended in this way.
http://www.jandecaluwe.com/Tools/MyHDL/manual/model-structure.html

People who have to decide whether MyHDL will used
for a project or not would like to see even more, a proof, e.g. a
complete project,
http://myhdl.jandecaluwe.com/doku.php/projects:phoenixsid_65x81

multiple clock domains,
http://www.jandecaluwe.com/Tools/MyHDL/manual/intro-hier.html

individual delays on signals
http://www.jandecaluwe.com/Tools/MyHDL/manual/ref-sig.html

asynchronous logic handling come in my mind.

From reading the introduction:

http://www.jandecaluwe.com/Tools/MyHDL/manual/intro.html

it will be clear that the MyHDL simulator is just an event-driven
simulator, in good old Verilog and VHDL tradition.

Jan