VHDL refactoring tools

[Wolfgang Grafen]

Actually not. The software folks who practice agile development insist on
incremental development, frequent testable deliverables and designing in
absolutely no more than is required for the current deliverable.

Agile development - just another buzzword, and even worse, nothing new.
Long before all but even more methods were described by Summerville
which had been a standard work for a time.

I have read through all of their ideas and what gave me the rest was a
contribution of a speaker on last EuroPython conference 2007. Optimum of
pair programming is about 45 minutes! Pair programming is very
exhaustive, and our problems are difficult enough that nobody is able to
work on another problem every 45 minutes. The idea is that after 2 weeks
working you need your holidays for recovering...

Extreme programming is about delivering a working framework in a short
time, programming hardware is to deliver a fault free environment after
a short time, and this is a huge difference. It does not cost the world
to fix a software error afterwards, but for hardware, it is. A software
error which hits the user every 20 minutes could be a hardware error
which occures every millisecond, and as hardware is not operated
interactively in many cases there are not easy workarounds.

I have read about the admiration about the relyability of good designed
hardware, and a group wanted to initiate "IC like software design".

It is not that we can't learn from modern software design, but the
quality of our designs depend only on excessive testing, and regression
tests. This is often not standard in software design, also not always in
FPGA design but for the multi million gates ASIC everything else is a no
no. As testing is often 80% of effort or more, the time to write the
functional code can be neglected. Real advances go hand in hand with
testing.

Research in the past has shown that not the language makes you
efficient, but the workflow. This could be agile development, of course,
but in an adopted way. For verifying hardware we have very advanced
methods software engineers can dream of. When reliability is concerned,
software can learn from an ASIC design flow. That means that you can be
beaten by antiquated methods any time, as long the working group is
familiar with it. A failure on a big ASIC means costs of 1Mio$+ and
delay of half a year. In the past we could manufacture ASICs like this
without functional failure. Show me any software as reliable as this.

Best regards

Wolfgang

 

[Mike Treseler]

I disagree in that it can (should) encourage design reuse.

I was agreeing with Jonathan that excessive
*internal* structure inside my own code,
also slows me down.
I agree that the more useful top entity ought
to have a simple, well-documented interface.

-- Mike Treseler