which commercial HDL-Simulator for FPGA?

[SynopsysFPGAexpress]

Software C/C++ (and other programming languages, too) have been
doing this for YEARS. Microsoft calls its solution "intelliSense".
It's in Developer Studio (VC++/VC##, VB.net/etc.).

The first time you (sucessfully) compile the project's source-code,
the class/variable browser registers every user-defined identifier
(typedef, class, function, struct, union, built-in type int/float/char) with
the editor.

Then, as you type source-code, the browser pops up a 'helper'
box. For function-calls (including the C/C++/Windows standard
library), it shows the argument-names and their data-type. I guess
you could call it dynamic annotation. You can jump to the definition
of the object under the cursor, at any time. (For standard library calls,
this is less useful -- most of the compiler header-files are unreadable
jibberish.)

As long as we are talking about our "wish list", I would also like an
editor that was smart enough to complete words and sentences in my
HDL. There are any number of ways that a program can track what you
are doing and try to anticipate your actions as you type. For
example, if I am creating a clocked process and typing an assignment
for a signal or variable , it would be nice to have the software know
that it needs a definition and an initialization in the reset portion
of the process. So as soon as I enter the assignment, it would take
me to the appropriate spot for the definition and start it for me to
complete followed by the same for the initialization in the reset
section of the process.

If I am typing a "with" statement, I want the software to see the word
"with" and put the rest of the structure on the screen for me to fill
in the blanks. I find all the typing to be tedious and error prone,
not to mention that after all these years, I still don't have the
syntax memorized and keep a small stack of books by my elbow.

Yeah, intelliSense does this for many contexts.
Though it sounds like you additionally want some form of AutoCompletion,
combined with context-sensitive editing.

 

[Kim Enkovaara]

So in either of these, you typically simulate and have all signals dumped to
a huge output file (using $dumpvars(0); $dumpon; for vcs or $shm_open(...);
$shm_probe(..); for ncsim). Then you can explore the design hierarchy and
choose which signals to view in vcs -RPP or simvision. The same is true for
even icarus verilog with gtkwave.

In my mind this might work for small designs, but the huge amount of
signal logging slows down the simulation. I usually like to log just
part of the signals needed, which is the normal way Modelsim works.
I never understood the way vcs liked to work, it felt so unintegrated
(in the past, the new GUI is and quite good copy of modelsim gui )

However with modelsim it looks like there is no way to do this. Instead,
when you add a signal to the viewer in the GUI, it re-runs the entire
simulation to get the new signal. Am I missing something or is this really
how it works? I can't believe that it would really work this way.

In the beginning of simulation just add
"log -r /dut/interesting_module/*" and after that you can add signals
from that block also after the simulation to the viewer.

And you can also open the wave from the GUI after the simulation, or
open many different waves logged from different places and merge or
compare them in the GUI (open dataset functionality etc)

(Also the crippled free modelsim is slower than icarus).

And I have seen Modelsim SE to be much faster than VCS in some designs.
Each design is different beast in terms of simulation speed and what
simulator is the fastest. Unfortunately none of the free simulators
support mixed language simulations, and almost all of the designs
I see commercially are mixed language, so it's quite hard to
test the speed differences.


--Kim

 

[Martin Thompson]

If I am typing a "with" statement, I want the software to see the word
"with" and put the rest of the structure on the screen for me to fill
in the blanks. I find all the typing to be tedious and error prone,
not to mention that after all these years, I still don't have the
syntax memorized and keep a small stack of books by my elbow.

Emacs. My problem now is that I have no idea what the syntax of VHDL
is, so if I have to write some from scratch in notepad, I can't
remember how to do it! I just type "proc" hit space and then I get
asked questions to fill in the rest of the template.

Just think how nice it would be to have the editor add the appropriate
conversion function when you type an assignment between incompatible
signals. No error message telling you that you need to convert that
integer to an unsigned, it just adds the conversion!

That'd be nice, but I kind of like the idea that I have to think about
it to stop me doing stupid things.

Having it magically use the right "<=" or ":=" depending on what's to
the left of it would be neat though... and a function to convert
between variable and signal I would find handy as well. I wonder if
my elisp skillz are up to that?

I hate to use a microsoft product as an example of the "right" way to
do anything, but the version of Word that I use does a pretty good job
of completing words for me sometimes.

Again, Emacs does a reasonable job of tab-completion on most things.

Learning Emacs was (still is - it'll never stop one of the most
productive thigns I've ever done. Even though it felt horrible for
the first 4 weeks or so!

[Followups trimmed to VHDL only]

Cheers,
Martin

 

[SynopsysFPGAexpress]

I've used this methods for many years for large ASIC designs. It slows
down the simulation, but I find this much more effective than running
the simulation again. Also it's more cost effective to release the
expensive simulation license and use the cheaper waveform viewer for
debugging. You can even run the simulations during the night and have
the VPD (TRN, SST or whatever you prefer) files waiting for you the
next morning.

For e/Specman and Systemverilog-TB debugging, the Cadence/NCsim
doesn't log dynamic-objects to the TRN/SST file. So you pretty much
have to do most debugging interactively (if you want to see Systemverilog
objects/queues/dynamic-arrays, etc.), with the full license checkout of
the simulator.

I'm not sure how that compares to Mentor Questasim or Synopsys VCS.