Why Doesn't VHDL Have a Wildcard Sensitivity List?

[backhus]

I fear not.  'all' is already a reserved word in every
version of the VHDL standard that I know of. (Think of
"use ieee.std_logic_1164.all;")

Cute idea, though.

Hi Jonathan,
*$%&! You're right, of course.
My only excuse is that the library stuff is handled by templates in
99.9% of my sources.

Sorry everybody for causing confusion.

Regards
Eilert

 

[rickman]

Again, because functions don't have sensitivity lists of course!

Still, they are guaranteed to have combinatorial semantics as
they can't have side effects in VHDL.

So in regards to hiding the "wires", they are not different at all...

Rick

 

[Mike Treseler]

So in regards to hiding the "wires", they are not different at all...

This thread is about the vhdl process sensitivity list and how to avoid
simulation problems if I use it for anything other than the clock
or reset inputs. This question has been answered.
The "wires" issue is a red herring.

http://en.wikipedia.org/wiki/Red_herring

By "wire hiding" I mean that by using a single process
description using variables, there are only port inputs
and outputs in the logic description.
Everything goes in one box -- the entity.
There are no internal "directions" to worry about,
other than code going from the top to the bottom of the page.

In a multi-process description,
I have two or more process boxes inside the entity,
each with inputs and outputs.

I claim that not having to worry about connecting internal
"outputs" together in my description is a side benefit *for me*
of this description style.

-- Mike Treseler