VHDL

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comp.lang.vhdl
A
order of signals in the ncsim waveform window
  • anupam
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0
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1K
anupam
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F
configuration question
  • fg
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3
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912
fg
F
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Representing INF in a real?
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3K
sharp
S
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Hardware implementation of Safer+ algorithm blocks 'e', 'l'
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Rag
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Running testbench simulation problem with Quartus II 4.2 and Modelsim 6.0d
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3
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5K
Mike Treseler
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Generate your way through the Verification quagmire
  • paddy3118
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5
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978
Mike Treseler
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Recursive function to generate mux output
  • Edward Watts
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6
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5K
Edward Watts
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I
Ques on HDL: Please help
  • Ignoramus
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1
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943
jens
J
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Reset Sync style
  • Rick North
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13
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2K
kameshwar_kaushik
K
M
please very urgent help required
  • my_messenger2006
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1
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kameshwar_kaushik
K
M
DCT URGENTLY REQUIRED
  • my_messenger2006
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0
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my_messenger2006
M
M
DCT REQUIRED URGENTLY
  • my_messenger2006
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0
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my_messenger2006
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J
Reference Manuels
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1
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690
Mike Treseler
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D
New alternative to CPLD and basic FPGA
  • Donato Pace
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3
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1K
Andy Peters
A
A
access internal signal on top level in VHDL
  • anupam
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2
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7K
Ralf Hildebrandt
R
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Help>Multiplier Code > State Machine Style > VHDL
  • kameshwar_kaushik
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0
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3K
kameshwar_kaushik
K
I
ISVLSI 2006 - Call for Participation
  • ISVLSI06
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0
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842
ISVLSI06
I
R
CFP: 2006 MAPLD International Conference
  • Richard B. Katz
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0
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1K
Richard B. Katz
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Adding constraints in Simplify and Altera Quartus
  • Juan Carlos Allica
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2
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1K
Noway2
N
A
using 2 diffrent clock rates in a design.
  • Abs
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0
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847
Abs
A
O
Benchtest dependign on configuration
  • Olaf Petzold
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3
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608
Mike Treseler
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D
Message Base
  • David Binnie
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1
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711
Mike Treseler
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?
"signal does not hold its value outside clock edge"
  • =?iso-8859-1?q?Guilherme_Corr=EAa?=
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5
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10K
=?iso-8859-1?q?Guilherme_Corr=EAa?=
?
P
how to include pre-compiled macro
  • Pasacco
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0
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1K
Pasacco
P
F
LED decoder with CoolRunner II
  • Flemming Hansen
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5
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2K
Mike Treseler
M
E
Help! Signed Number Representation in Xilinx Testbench Waveform
  • Emel
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2
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5K
Brian Drummond
B
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Separating control and data paths
  • crazyrdx
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4
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1K
Mike Treseler
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F
How in Design Compiler disable writing out "Assign" statement into the netlist?
  • Frank
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2
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5K
Jerry Avins
J
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integer to floating poit converter
  • mmt1
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1
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4K
Mike Treseler
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T&M Verilog Reference
  • hdl_book_seller
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0
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752
hdl_book_seller
H
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floating point
  • mmt1
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1
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1K
Uncle Noah
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Xilinx V-4 BRAM
  • Brad Smallridge
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0
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4K
Brad Smallridge
B
J
Data error
  • john
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3
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919
jtw
J
J
DTFT or Goertzel in VHDL
  • jpdullius
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1
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3K
jens
J
D
Synthesis erron for "bit'val" attribute....plz chek
  • Dunce by face...
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1
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1K
Dunce by face...
D
A
TCL CODE WITH VHDL
  • AAA
2
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22
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8K
AAA
A
M
What's wrong in this VHDL subtraction?
  • mweb
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3
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26K
Eric Smith
E
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generic serial to parallel IO module
  • eddie
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4
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4K
Duane Clark
D
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Adaptation from PI output to PWM???
  • nesppi
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0
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1K
nesppi
N
A
problem with two sources
  • arti
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9
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2K
Andy
A
C
How to Write FSM???
  • cafm
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5
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2K
Francisco Rodriguez
F
J
very large no. of interconnections
  • junaid.ece
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0
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643
junaid.ece
J
A
Call for Papers: MSV'06 (part of WORLDCOMP'06)
  • A. M. G. Solo
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0
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897
A. M. G. Solo
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J
Generic design using generate statement
  • junaid.ece
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3
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7K
Rob Dekker
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FIR with complex coefficients- VHDL implementation
  • Emel
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1
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7K
Mike Treseler
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C
avoiding race
  • crazyrdx
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3
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1K
jens
J
L
I can not figure this vhdl logic out, help.
  • logia
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6
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1K
jens
J
M
small question
  • moonlight
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1
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688
patrick.melet
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Questions about Async FIFO
  • kedarpapte
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1
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14K
hdlcohen
H
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VHDL-AMS question
  • Aravind
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0
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1K
Aravind
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