VHDL

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comp.lang.vhdl
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use work.my_package.all-->what exactly meaning of this
  • Parthav
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4
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Mike Treseler
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Harware Engineer Level II and Senior positions Salary 60 K - Open
  • The job lady
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The job lady
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Book on VHDL basics and HDL based design
  • Brendan Illingworth
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2
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Ralf Hildebrandt
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is a digital filter necessary?
  • nesppi
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1
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980
reto.knaak
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Call For Papers: June 26-29, 2006, joint conferences in computer science, computer engineering & ap
  • A. M. G. Solo
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0
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A. M. G. Solo
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New to VHDL, Floating point arihmetic operators
  • jowe
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1
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Mike Treseler
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help to input array
  • ashu
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1
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4K
jens
J
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Why 'a plurality of N' must be used for 'N' in patent claims
  • wtxwtx
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11
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soar2morrow
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DPRAM in VHDL with different bus width
  • reto.knaak
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4
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reto.knaak
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Coding style
  • Guest
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6
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1K
Rob Dekker
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Register initialization
  • Aji
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13
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Colin Marquardt
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Study material for logic design
  • salah.kazi
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2
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salah.kazi
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I need help for RAM coding In verilog
  • apssingh
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1
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1K
Ajeetha
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IEEE/NASA Adap. HW Conf in Istanbul
  • hugurdag
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1
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2K
Andrew Greensted
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Don't care and optimization
  • Andrew Greensted
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3
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4K
Andrew Greensted
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function with 2d return type
  • Maki - \(Remove 123 to mail me\)
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2
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865
Maki - \(Remove 123 to mail me\)
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FPGA interface design to access the BRAM
  • pingluns
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0
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pingluns
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regarding look up table
  • onkarkk
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2
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829
Duane Clark
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Independent processes
  • john
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3
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850
john
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help
  • nesppi
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2
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865
nesppi
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Programming Xilinx PowerPC
  • ma
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11
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5K
Michael Thomsen
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Breaking of Frames in Ethernet switch/Mux
  • kedarpapte
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0
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kedarpapte
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Presto VHSL can't find the IEEE library!!
  • akun
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0
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1K
akun
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Independent processes
  • john
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0
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790
john
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A
RTL for Z8000 series CPU?
  • ajcrm125
2 3
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40
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5K
Tobias Weingartner
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Case statement syntax
  • Fred
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2
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11K
Fred
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how to initialize 2 BRAM (RAMB16_S18)
  • Pasacco
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5
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5K
Thomas Stanka
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Help! FIR Filter - MATLAB fdatool - VHDL
  • Emel
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0
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4K
Emel
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Newbie: ieee.math_real + ghdl
  • Andreas
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10
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4K
Phil Tomson
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Asynch. signal
  • john
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0
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886
john
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Coding style, wait statement, sensitivity list and synthesis.
  • AG
2 3
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45
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13K
Andy
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Image processing libraries
  • john
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3
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1K
jens
J
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Asynch. signal
  • john
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0
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810
john
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extension_pack
  • MB
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0
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MB
M
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Generic controlling sync/async reset
  • Niv
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9
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Mike Treseler
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Dual-Port RAM Simulation in ModelSim
  • Keith Blankenship
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1
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3K
Mike Treseler
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eliminate concurrent statement
  • Aji
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2
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3K
Aji
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Plugin Eclipse
  • you.writeme
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1
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3K
Frank
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The 'impure' construct
  • Alif Wahid
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2
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12K
Reiner Huober
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Designing a I2C slave using Spartan 3E and VHDL
  • LRCR
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2
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9K
Konstantin Schmidt
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Warnings DCM Spartan3
  • u_stadler
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1
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2K
Marco
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Data Decoding at 10 Gbit/s
  • Martin Schimmelpfennig
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4
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3K
JosephKK
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What is the difference betwee 'Method' and 'Apparatus' in a patent claim area
  • wtxwtx
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10
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4K
wtxwtx
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Inferred latches questions
  • stoyan.shopov
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3
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10K
Ralf Hildebrandt
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real-time compression algorithms on fpga
  • Melanie Nasic
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19
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5K
Thomas Rudloff
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very simple question on Cos and Sin
  • aj
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10
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6K
james
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Macrocell usage
  • Georg Gläser
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2
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1K
Ivan Wagner
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suggest a project
  • Kusuma
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6
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869
aaaaaa
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VCDEdit
  • Naren
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0
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1K
Naren
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Clock Signals
  • u_stadler
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5
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4K
Tim Good
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