VHDL

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comp.lang.vhdl
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Image processing using VHDL
  • vgs
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vgs
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Vhdl codes for edge detection
  • vgs
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vgs
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vhdl codes for edge detection
  • rajesh yadav
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1
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jeppe
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Would you like the alternative to Zero Ohm?
  • valtih1978
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1
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hdlcohen
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Is this an LRM thing, or Modelsim Bug?
  • Tricky
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2
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Martin Thompson
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Configuring FPGA bulk chips
  • Insight Realm
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2
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Nick Anghelidi
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trouble connecting an out std_logic_vector port to aggregate of signals
  • ihk
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1
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Pontus
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regarding thesis
  • guranditta guranditta
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1
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Thomas Stanka
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a simple CPU Design with some basic operations
  • vhdl_addicted
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4
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jesvant
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A free lunch
  • Jan Decaluwe
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0
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Jan Decaluwe
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How do you introduce delays into 3-state (bi-dir) lines?
  • valtih1978
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11
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valtih1978
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Best advice for FPGA/VHDL beginner?
  • KK6GM
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13
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amit_k
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how to start FPGA's
  • pavan
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7
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8K
amit_k
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VHDL and System Verilog Assertions
  • thunder
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1
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Jonathan Bromley
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help with binary decoder
  • majmoat_ensan
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1
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eliascm
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Ethernet and TCP/IP proto in vhdl
  • =?ISO-8859-2?Q?Przemys=B3aw_Staniszewski?=
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8
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alainsan
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PSL book suggestions
  • thunder
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2
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Matthias Alles
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PSL assertion book suggestion
  • thunder
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0
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thunder
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automating bringing of signals in hierarchical VHDL model to toplevel entity
  • fearg
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10
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Hendrik Eeckhaut
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Regarding to the DUT configuration in testbench
  • JSreeniv
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1
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sri.cvcblr
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Assertions
  • thunder
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4
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sri.cvcblr
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Monitoring inout signal transactions
  • valtih1978
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1
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Guest
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Is Partial Record Assignment Possible?
  • Sudoer
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12
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Jonathan Bromley
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Indentation in Posted Code
  • eliascm
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3
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flymolo
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Exponential code in VHDL
  • Zaid Al-Hilli
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6
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5K
Zaid Al-Hilli
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Help! Xilinx ISE fails to use std_logic_1164!
  • delightfulbaker
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3
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3K
julianm
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3D-Port of natural range <>
  • vollbr0t
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0
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vollbr0t
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1to8 Demux code, can you look plz
  • majmoat_ensan
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6
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eliascm
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error: (infix expression) for formal "din" is not a globally static expression
  • tomer
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0
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tomer
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Design Built-in Self Test
  • abhishekshishodia
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1
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KJ
K
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Matlab Online Training at Embedded Wings
  • ewings
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0
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ewings
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Attribute that shows if signal is clocked or not?
  • Colin Beighley
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2
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Gabor
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Conditional declarations
  • Colin Beighley
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4
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KJ
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MUX with generate statement
  • RADNOR
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3
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9K
RADNOR
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Synthesis of multiple wait statements per VHDL-200X
  • Colin Beighley
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8
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6K
KJ
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What is use of filters??
  • maheshkumar0459
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1
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flymolo
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vhdl model of microprocessor
  • Haridas
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1
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jeppe
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empty array litteral
  • JR
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1
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Tricky
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empty array
  • reinauld
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reinauld
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Are there technical reasons why Emacs is better than an IDE?
  • Philippe Faes
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15
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Philippe Faes
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Can any one help me in designing FIR filter in VHDL??
  • maheshkumar0459
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2
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maheshkumar0459
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wait for argument a variable?
  • Shannon
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14
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2K
Jonathan Bromley
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one signal set ffrom two processes .....
  • Gerhard
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17
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Alessandro Basili
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Synthesis of 'X'
  • Colin Beighley
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3
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1K
Martin Thompson
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[ANN] HercuLeS high-level synthesis tool
  • Nikolaos Kavvadias
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0
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Nikolaos Kavvadias
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Best way for average out
  • Old Siam Sir
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3
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flymolo
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job offer fpga designer genova
  • r_hwdesigner
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r_hwdesigner
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Combined AFTER and WHEN statement
  • JB
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1
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1K
hssig
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can any one help me in VHDL codes plz
  • majmoat_ensan
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3
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2K
KJ
K
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Who is interested in taking the Synthworks' VHDL Testbenches and Verification Course?
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0
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1K
[email protected]
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