VHDL

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comp.lang.vhdl
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VGA problem with timing
  • stepi
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stepi
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VGA problem with timing
  • stepi
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stepi
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VGA problem with timing
  • stepi
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stepi
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[Help request] VHDL to Graphics
  • Netlopa
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5
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Mike Treseler
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modified booth multiplier
  • deepthi
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deepthi
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Anti-benchmarking clauses
  • Philippe
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5
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Paul Colin Gloster
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looking for 14 pin flying lead cable
  • rich12345
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1
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NeedCleverHandle
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Vhdl operations
  • cally_cally
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3
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joris
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A. G. Lisi's E8 model may be showing us what both our space & timereally are.
  • fitz
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fitz
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are the next things are synthesizable?
  • Kapish
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eliascm
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Can anyone think of a workaround - Ideally I want to pass an accesstype into an entity (not for synt
  • Tricky
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7
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JimLewis
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trimming of wanted (useful) signals in XILINX board what is the problem of my code
  • corin.otesteanu
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1
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corin.otesteanu
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Conditional signal assignment or process statement
  • devas
2 3
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40
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Andy
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Proper index type to access an std_logic array
  • sylwa
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2
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sylwa
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vhdl code for FIR Filter using wave-pipelining
  • deepthi.reddy.912
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deepthi.reddy.912
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How to alternately choose to run questa or riviera?
  • Chandan Choudhury
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Chandan Choudhury
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[Fwd: Vhdl dynamic generation]
  • Mike Treseler
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2
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abida
A
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baudrate generator
  • kiran423
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9
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5K
kiran423
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Is this a VHDL limitation, or Modelsim bug
  • Tricky
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3
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Peter Spjuth
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Simon Game - VHDL
  • Leconte
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1
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4K
jeppe
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Signal Generator using FPGA and DAC
  • Sheetal
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13
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Geethu
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Incorrect simulation of a shift register in multiplication
  • Joseph
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3
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Andy
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Modelsim on a Remote Desktop
  • world_tan
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1
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world_tan
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Question on Comparing two std logic vecter
  • Tha
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4
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eliascm
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ISE10.1 in WIndows 7 Pro (64-bit).
  • world_tan
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0
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world_tan
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syntax error? help!
  • Somnium
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1
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joris
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"Clockless" computing
  • Harold Aptroot
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1
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backhus
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Reading in values from file
  • bubbagumper6
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bubbagumper6
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Sequential microprocessor code to vhdl - easy conversion tips?
  • Oliver Mattos
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6
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Kellyng91
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Sorting top 3 maximum values
  • amey
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1
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jeppe
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urgent need
  • abida
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1
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jeppe
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Array pipeline
  • hssig
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2
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hssig
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8254 mode 2 divide by n counter
  • least.square
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3
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least.square
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please please please take attention to my letter
  • mera
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7
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mera
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Synthesis of Logic on Non-boolean Constants
  • rickman
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9
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rickman
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VHDL and Image processing.
  • Amit
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9
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8K
John123
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parse error, unexpected PORT, expecting OPENPAR or TICK or LSQBRACK
  • krishlal925
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2
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joris
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Parse error with VHDL in Xilinx Tools?
  • leo89vjl
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2
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jaga
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Odd Simulator Error
  • rickman
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2
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Brian Drummond
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Style Request for Testbench with Bus Interfaces
  • M. Norton
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9
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Andy
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Numeric_std unsigned issues?
  • rman123
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2
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rman123
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only 7 days to go - 4th FPGA Camp - 6'Apr 2011 Silicon Valley
  • Vikram
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0
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Vikram
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PWM using FPGA
  • iceman
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10
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34K
mera
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new in vhdl - a little question
  • ee1
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1
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rman123
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sift-register
  • see-me
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see-me
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counter help
  • see-me
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3
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joris
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storing .txt file in an array..
  • gopal.master
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gopal.master
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counter help
  • see-me
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see-me
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constant integer to unsigned casting
  • Limor
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Limor
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Loosen timing on a net (xilinx)
  • rodentje
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0
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rodentje
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