VHDL

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comp.lang.vhdl
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ngd2edif vs. ngc2edif
  • valentin tihomirov
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valentin tihomirov
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Block Ram Problem
  • Tim O' Sullivan
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1
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871
Mike Treseler
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renoir shift syntax
  • dan list
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1
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1K
Mike Treseler
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Convert decimal number in binary number
  • makok
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1
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9K
Anders Hellerup Madsen
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Driving INOUT ports
  • Mike Nicklas
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0
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1K
Mike Nicklas
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VHDL Compilation error. Please help
  • raju
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4
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3K
raju
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Comparator and minimum value address
  • sunil
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4
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1K
Ralf Hildebrandt
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Simulation Model for SRAM
  • ALuPin
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2
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6K
FMF
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Random logic verilog gate netlist generator
  • Simon S. IBM
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3
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5K
B. Joshua Rosen
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regarding synchronization
  • prav
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5
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2K
Jos De Laender
J
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Hexadecimal to Binary File Conversion Utility
  • Victor Hannak
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0
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9K
Victor Hannak
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Open Drain or Tri-state???
  • Analog Guy
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1
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4K
fabbl
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Are generics and ports static names?
  • David Jones
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0
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1K
David Jones
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ANN: Graphical Testbench Tool Download
  • Scott Thibault
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2
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1K
Scott Thibault
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Barrel shifter compilation in QuartusII
  • ALuPin
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0
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1K
ALuPin
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Rotate by variable
  • Patrick Moore
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18
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6K
Ray Andraka
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4 stage register or fifo
  • salman sheikh
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2
Views
969
salman sheikh
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VHDL newbie
  • Joseph A. Zammit
Replies
7
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994
Jonathan Bromley
J
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adaptive viterbi decoder design
  • sunil
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1
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1K
deepak_ddn
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Invitation to Register in ISQED04
  • INFO
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0
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892
INFO
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vhdl 2 blif prob
  • paraag
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0
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2K
paraag
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can we implement LIFO using SRL16 ???
  • Oleg
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5
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3K
Ray Andraka
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Good books/tutorials on VHDL?
  • Chaos Master
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1
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1K
Kwaj
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Propagation delay trought a control signal "SEL" of a MUX
  • Oleg
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1
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1K
Francisco Rodriguez
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Liaison infra-rouge à 9600 Bauds (IRDA)
  • Arnaud
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1
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1K
Iwo Mergler
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declaring signals depending on generic parameters
  • valentin tihomirov
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1
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1K
Jonathan Bromley
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ModelSim question/checking the value of a variable
  • kwaj
Replies
3
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4K
Grigorios Angelis
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Barrel shifter
  • ALuPin
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1
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2K
Jonathan Bromley
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Using loop vars in a testbench
  • sku11monkey
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2
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1K
Grigorios Angelis
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Actual is not a globally static expression
  • valentin tihomirov
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7
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23K
Jonathan Bromley
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Bit-Stuffing on parallel 8 bit data
  • kumar
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8
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5K
Vikram
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Configurable Entity Statement
  • rAinStorms
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1
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1K
Jonathan Bromley
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rounding to integer
  • valentin tihomirov
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2
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19K
Jonathan Bromley
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Digilent Spartan II demo board push button
  • Clyde
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2
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3K
Clyde
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FIR filter design + COE file
  • Yttrium
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1
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4K
Hari
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constants declaration
  • Benjamin Todd
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2
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7K
Benjamin Todd
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Newbie
  • smilo
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1
Views
909
fabbl
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?
Problem with Spark wiredOrInt
  • =?ISO-8859-1?Q?Dominik_Fr=F6hlich?=
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0
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786
=?ISO-8859-1?Q?Dominik_Fr=F6hlich?=
?
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Vsim - graphical simulation environment?
  • kwaj
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2
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1K
kwaj
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fixed point multiplier in VHDL
  • Viswan
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9
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14K
Ray Andraka
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vhdl code for 8085
  • dipu bhaskar
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2
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3K
Ray Andraka
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comment faire une détection de niveau haut ou "1" en vhdl ?
  • Arnaud
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2
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5K
Amontec Team, Laurent Gauch
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Timing Models; here Transport
  • Thomas K. Balthasar
Replies
1
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922
fabbl
F
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Size of an array
  • kwaj
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2
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9K
Charles M. Elias
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Active-HDL, bitmap, simulation, Tcl/Tk
  • Stein Kjølstad
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1
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1K
valentin tihomirov
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power calculation in fpga
  • sunil
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2
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2K
Brendan Cullen
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Sytem date
  • Monika Talwar
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2
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1K
Srinivasan Venkataramanan
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question of style
  • valentin tihomirov
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4
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782
Thomas Stanka
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Arithmetic Libraries
  • ALuPin
Replies
1
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967
Ralf Hildebrandt
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Dividing Real Numbers?
  • kwaj
Replies
2
Views
2K
kwaj
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