VHDL

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comp.lang.vhdl
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product of real and (integer)(after converted to real one) value - vhdl found fatal error
  • senthil
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5
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3K
senthil
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time set up
  • Andres
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1
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753
Mike Treseler
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C
How can I have multiple drivers of one inout port?
  • cruzin
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2
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7K
PO Laprise
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compiler of language C to openrisc processor with VHDL
  • Tony
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1
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2K
Mike Treseler
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Portability
  • Francisco Rodriguez
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2
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1K
fabbl
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Why do we hate variables?
  • Nicolas Matringe
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4
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5K
fabbl
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Loop exit
  • Niv
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4
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2K
Alan Fitch
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Newbie: what's the difference btn ':=' and '<='
  • jk
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8
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995
David Brown
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CFP: 2004 MAPLD International Conference
  • Richard B. Katz
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0
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1K
Richard B. Katz
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newbye and Sonata / open_file problem
  • Fred Bartoli
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2
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1K
Fred Bartoli
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Packages, Components ??? How to organize a design ???
  • Analog Guy
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8
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2K
Mike Treseler
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C
newbie question on VHDL
  • Chris sun
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2
Views
803
Amontec Team
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Convolution in VHDL
  • Hari
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3
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10K
Guest
G
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Synthesis errors?
  • Ken Morrow
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3
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1K
John Adair
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Non static border in Loop
  • Bochumfrau
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3
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924
Eyck Jentzsch
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QUES: Where can I find Xilinx M1 tools
  • Ted
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6
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1K
JoeG
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Bit-Level C Simulator
  • Kingsley Oteng
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4
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1K
Tuukka Toivonen
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help with if ...(probably very lame question)
  • Mariusz
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7
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1K
Sajan
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Why sensetivity list?
  • valentin tihomirov
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8
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1K
Kumaran Selvaratnam
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Input Delay and Hold Time
  • Anand P Paralkar
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4
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12K
Alexander Gnusin
A
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Mod (%) Function in VHDL
  • Kwaj
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7
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53K
jacky Renaux
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metastability
  • fabbl
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6
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1K
fabbl
F
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integer BCD converter in VHDL
  • nuessli
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1
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4K
Jeroen
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PLUS3 in VHDL
  • Rafa³ K³ysiewicz
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0
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738
Rafa³ K³ysiewicz
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A
what does the sim.
  • Attila Csosz
Replies
1
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771
Thomas Stanka
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C
What does nios-run do?
  • cruzin
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5
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2K
cruzin
C
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FOO
  • Wong
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1
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1K
Chenbo Liu
C
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Design Compiler "ACS" feature?
  • synop_user
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0
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1K
synop_user
S
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please help! state machine
  • Simone Winkler
Replies
6
Views
958
stephen henry
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Synplicity Synthesis of VHDL module
  • salman sheikh
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0
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2K
salman sheikh
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Testbench HowTo Apply Hex Values from a File
  • Markus Meng
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1
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3K
Mike Treseler
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VGA
  • EyeOfRa
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1
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2K
kermit6306
K
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Quantization levels of received symbol for viterbi decoder
  • sunil
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1
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2K
Oleg
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Integer or STD_LOGIC_VECTOR
  • jk
Replies
3
Views
12K
Amontec Team, Laurent Gauch
A
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Libraries, packages and synthesis problems!
  • Michael Nicklas
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4
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6K
kengpk
K
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explanation
  • Mariusz
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1
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1K
tbx135
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E
"non-blocking" read in VHDL?
  • Edward L. Hepler
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0
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1K
Edward L. Hepler
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subtype for integers
  • Hari
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5
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2K
Jim Lewis
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How to generate a CSA tree?
  • Sleep Mode
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1
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3K
fe
F
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image file reading in vhdl
  • suneetha
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2
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7K
Martin Thompson
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with ... select syntax
  • Hernán Sánchez
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3
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54K
Jim Lewis
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Openmore checklist
  • sean
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2
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1K
sean
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Cypress Warp2 ROM Module File Format
  • Brad Smallridge
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1
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1K
Brad Smallridge
B
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How put a signal value into REPORT ?
  • ALuPin
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2
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3K
VhdlCohen
V
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chirpz transform in VHDL
  • Hari
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1
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1K
tbx135
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More synchronization problems
  • Simon
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1
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1K
tbx135
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Newbie Question: No Vsim, Vlib etc in my ModelSim
  • jk
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3
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4K
Kwaj
K
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SystemC
  • Fred H
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1
Views
1K
Alan Fitch
A
A
Adding internal signals in Modelsim
  • ALuPin
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5
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4K
ALuPin
A
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Counter help
  • salman sheikh
Replies
2
Views
1K
Ralf Hildebrandt
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