VHDL

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comp.lang.vhdl
M
reading the stimuls from input file
  • my24101974
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2
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885
VhdlCohen
V
A
Hold Time Check Using a Procedure
  • Anand P Paralkar
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2
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2K
Renaud Pacalet
R
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will Synopsys Design Compiler automatically collect common sub expression to do intelligent optimiza
  • walala
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6
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1K
Renaud Pacalet
R
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R: pullup on inputs
  • Max
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0
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1K
Max
M
M
pullup on inputs
  • Max
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0
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1K
Max
M
A
atan in a FPGA
  • Andi
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2
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5K
Acciduzzu
A
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problem with ise webpack 6.1
  • Max
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1
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1K
Marc Guardiani
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Am I right in my VHDL code? Synopsys DC runs for ever...
  • walala
Replies
8
Views
2K
Ralf Hildebrandt
R
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NEWBIE: Command line synthesis with Webpack
  • Torquemada
Replies
1
Views
916
Falser Klaus
F
S
dummy projects in VHDL/Verilog
  • shumon
Replies
1
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13K
Jim Wu
J
P
MOD function synthesis
  • praveen
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1
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2K
Allan Herriman
A
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how to implement gated clock and gated partial circuit in VHDL?
  • walala
Replies
3
Views
12K
Roadie Roger
R
R
delta delay..
  • Ramakrishnan
Replies
4
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7K
Mike Treseler
M
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VHDL Simulator Options
  • Mike Kopp
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3
Views
1K
FE
F
A
Integers only as generics?
  • Acciduzzu
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4
Views
2K
Allan Herriman
A
L
How to print a long unsigned ?
  • Lolo
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3
Views
2K
Jim Lewis
J
L
equivalent types in different packages
  • Lolo
Replies
3
Views
1K
Lolo
L
M
buffer port
  • Max
Replies
1
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3K
Egbert Molenkamp
E
M
SRAM vs Cache
  • Michael
Replies
4
Views
9K
Mario Trams
M
P
modeltech(modelsim) for linux platform, license?
  • ParkSungJae
Replies
0
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2K
ParkSungJae
P
M
dimension of an integer
  • Max
Replies
4
Views
1K
sean
S
A
Type Error ??!! Any help
  • Ahmad
Replies
3
Views
803
Ahmad
A
B
'STD_LOGIC_VECTOR ' to 'unsigned' type casting
  • Ben Nguyen
Replies
6
Views
22K
Niv
N
S
Seeking Free ASIC Design Kit.
  • Slawek Grabowski
Replies
4
Views
3K
Guest
G
C
SystemVerilog: "logic" or "ulogic?"
  • Cliff Cummings
Replies
7
Views
5K
cc0139808
C
M
avoid the warnig
  • Max
Replies
6
Views
1K
Jim Lewis
J
M
useless synthetized blocks
  • Max
Replies
1
Views
855
Mike Treseler
M
B
Using LUTs for array of coefficients
  • Bob
Replies
1
Views
1K
Jim Lewis
J
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R: useless synthetized blocks
  • Max
Replies
1
Views
810
Jim Lewis
J
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I'm looking for Altera Quartus II 3.0 License file
  • dong seok huh
Replies
1
Views
2K
Bill Grubbs
B
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Is "integer" a keyword of VHDL?
  • John
Replies
4
Views
8K
David Jones
D
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FS: IKOS NSIM 64 Simulation Acceleration Hardware
  • Tristan Hunt
Replies
0
Views
2K
Tristan Hunt
T
D
Webpack Vs. ISE
  • Dave
Replies
10
Views
5K
Nial Stewart
N
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what's the difference between VHDL 93 CONCATENATION and VHDL 87 CONCATENATION?
  • walala
Replies
3
Views
6K
walala
W
K
Timing Diagram to HDL Translation
  • Kieran Francisco
Replies
9
Views
3K
VhdlCohen
V
J
Counter with carry out at embedded bit.
  • Jan Kindt
Replies
1
Views
2K
Jim Lewis
J
Y
Boundary scan clocking
  • Yves Tchapda
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0
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1K
Yves Tchapda
Y
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Event
  • Michael
Replies
2
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4K
Jim Lewis
J
M
Multi-Source
  • Michael
Replies
2
Views
2K
Dan RADUT
D
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Importing Structural VHDL into Cadence 4.4.6
  • Marcus Schaemann
Replies
1
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2K
Eyck Jentzsch
E
V
compilation error with ModelSim
  • Vincent
Replies
3
Views
2K
Jon
J
R
PCI core and Cyclone
  • Roberto Gallo
Replies
2
Views
1K
Roberto Gallo
R
M
Actel Desktop Schematic Viewer
  • Michael Dunbar
Replies
0
Views
1K
Michael Dunbar
M
M
OT: trouble with xilinx tool
  • Max
Replies
0
Views
786
Max
M
K
Question - aggregates..
  • Kot
Replies
4
Views
1K
Kot
K
M
Tristate
  • Michael
Replies
5
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2K
Charles M. Elias
C
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DDC design
  • Jan
Replies
2
Views
2K
Ray Andraka
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State machine: how to stay in a state?
  • David Lamb
Replies
1
Views
2K
MM
M
S
FFI against VHDL for test-benches
  • Spur
Replies
4
Views
3K
Hans
H
W
can I do such a simplest counter in VHDL?
  • walala
Replies
3
Views
15K
VhdlCohen
V

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