VHDL

Post thread
comp.lang.vhdl
M
I cannot simulate
  • Max
Replies
1
Views
1K
Jon
J
W
shall I reuse a variable/signal or not?
  • walala
Replies
1
Views
965
Jon
J
W
will Synposys Design Compiler support division by two's power and integer rounding?
  • walala
Replies
12
Views
3K
Jon
J
T
Is there any good book on PCI interface design?
  • tsj
Replies
4
Views
2K
Jon
J
K
How to run a zero-delay simulation in a design with a RAM?
  • Kelvin
Replies
0
Views
2K
Kelvin
K
W
NEWBIE ASKING FOR HELP! can anybody take a look at my Synopsys DC report?
  • walala
Replies
2
Views
2K
walala
W
K
Re: When do I always put a "else NULL" statement in my VHDL code?
  • Kelvin
Replies
1
Views
6K
Kelvin
K
G
VHDL switch model
  • Grzegorz Jablonski
Replies
0
Views
11K
Grzegorz Jablonski
G
C
bata takes too long with sun
  • Chuck Swart
Replies
1
Views
954
Chuck Swart
C
M
R: again on state machine
  • Max
Replies
1
Views
879
William Wallace
W
W
SOS! What can I do if Synopsys does not allow my statement?
  • walala
Replies
1
Views
1K
steve
S
W
MODELSIM cannot display the values of a variable?
  • walala
Replies
1
Views
1K
Kai Harrekilde-Petersen
K
W
How can I infer resource re-use in my VHDL code?
  • walala
Replies
4
Views
1K
walala
W
M
where to define a type?
  • Max
Replies
1
Views
862
Mike Treseler
M
J
Record, Enumeration & std_logic_vector
  • Jan Kindt
Replies
5
Views
3K
Allan Herriman
A
T
Open Source Vhdl Simulators?
  • td
Replies
1
Views
7K
Tuukka Toivonen
T
S
Integer to slv
  • stephen henry
Replies
4
Views
2K
Mike Treseler
M
E
Tool survey for syntax for formal => actual
  • eadgbe
Replies
3
Views
1K
eadgbe
E
M
conversions
  • Max
Replies
0
Views
1K
Max
M
W
what is wrong with my VHDL code? I am so dissappointed...
  • walala
Replies
3
Views
5K
Ralf Hildebrandt
R
W
Silicore adopts open source business model for semiconductor IP; releases SLC1657 uP core under LGPL
  • Wade D. Peterson
Replies
0
Views
1K
Wade D. Peterson
W
M
again on state machine
  • Max
Replies
4
Views
2K
William Wallace
W
S
switching problem
  • Simone Winkler
Replies
5
Views
1K
William Wallace
W
M
decoder
  • Max
Replies
2
Views
2K
Egbert Molenkamp
E
C
Design Flow: STA to Synthesis
  • Crimson_M
Replies
1
Views
2K
Brian Drummond
B
W
SOS! newbie question about synthesizable VHDL : synthesis run successfully but post-synthesis failed
  • walala
Replies
4
Views
2K
Technology Consultant
T
W
Are all the signals read in the process should appear in the sensitivity list of the process?
  • walala
Replies
3
Views
2K
Allan Herriman
A
K
Manipulating with the T1, T0 and TX in a SAIF file.
  • Kelvin Tsai @ Singapore
Replies
0
Views
1K
Kelvin Tsai @ Singapore
K
K
Synthesizing a design with RAM.
  • Kelvin @ Singapore
Replies
0
Views
1K
Kelvin @ Singapore
K
V
predefined function/library
  • Vincent
Replies
3
Views
2K
Egbert Molenkamp
E
S
ModelSim and the Xilinix web pack unisim libraries
  • Stephen Lohning
Replies
1
Views
2K
Barry Brown
B
W
what are the possible reasons that successful pre-synthesis simulation + successful synthesis = fail
  • walala
Replies
4
Views
3K
Ralf Hildebrandt
R
J
Question: inout signal assignment
  • John Potter
Replies
1
Views
3K
Renaud Pacalet
R
W
any VHDL books on low resource(throughput, area, power trade-off) design?
  • walala
Replies
0
Views
1K
walala
W
M
(newbie) processo or not process?
  • Max
Replies
7
Views
997
J. Bhasker
J
W
is function conv_std_logic_vector() synthesizable?
  • walala
Replies
2
Views
9K
Ralf Hildebrandt
R
W
How to get a slice of INTEGER type out?
  • walala
Replies
1
Views
3K
MM
M
K
Using "others" in if statement
  • Kot
Replies
11
Views
1K
Renaud Pacalet
R
W
Coding style to prioritize certain inputs
  • Willem Oosthuizen
Replies
5
Views
1K
Mike Treseler
M
S
function read_eeprom(addr); possible?
  • steve
Replies
3
Views
2K
Mike Treseler
M
C
A student's question
  • Chen Bin
Replies
7
Views
1K
Kot
K
M
array of component
  • Max
Replies
1
Views
986
Ralf Hildebrandt
R
M
(newbie) 2 read/write register
  • Max
Replies
1
Views
5K
eadgbe
E
M
warning?
  • Max
Replies
2
Views
3K
eadgbe
E
J
GHDL query
  • John Williams
Replies
6
Views
5K
Felix Bertram
F
W
newbie question about <= and :=? what's the difference?
  • walala
Replies
3
Views
2K
Egbert Molenkamp
E
S
Truth Table Implementation
  • shibu
Replies
3
Views
6K
Mario Trams
M
W
how to read and understand long written VHDL code?
  • walala
Replies
6
Views
4K
Marcus Harnisch
M
M
newbie question about decoder
  • Max
Replies
0
Views
1K
Max
M
W
Prioritising nets
  • Willem Oosthuizen
Replies
3
Views
1K
Renaud Pacalet
R

Members online

Total: 2,329 (members: 2, guests: 2,327)
Robots: 384

Forum statistics

Threads
474,158
Messages
2,570,882
Members
47,414
Latest member
djangoframe

Latest Threads

Top