VHDL

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comp.lang.vhdl
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Free VHDL Simulator
  • Basuki Endah Priyanto
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1
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7K
Tuukka Toivonen
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Verification Intern Positions Available
  • Recruit Interns
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0
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2K
Recruit Interns
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VHDL Prettifier for Windows
  • Matt
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4
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3K
fred
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VHDL Packages
  • Sandeep
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1
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6K
Egbert Molenkamp
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Yet another modelsim problem
  • Thomas
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1
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2K
K Mussatt
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write data to Sram and then read to PC
  • sarah
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1
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2K
Jan Panteltje
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XILINX FPGA project
  • Davo
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0
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7K
Davo
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Long simulations
  • Pedro Claro
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0
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1K
Pedro Claro
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Error please Help
  • Isaac
Replies
4
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4K
Jim Wu
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Configurable hardware thro' VHDL
  • dutta
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0
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2K
dutta
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Internship/Co-op
  • KaRtiK
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0
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2K
KaRtiK
K
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any good books for studying VHDL with meaningful examples?
  • walala
Replies
1
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2K
Mike Treseler
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DDR/SDR-SDRAM Bank Switching Doubt
  • Abdul K Shaik
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1
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3K
David Jones
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Inquiry about a VHDL signal tracer tool...
  • Debashish
Replies
3
Views
3K
Mike Treseler
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Initial value on ports
  • Marek Ponca
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0
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4K
Marek Ponca
M
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manchester encoder
  • Ronny Hengst
Replies
4
Views
8K
Jonathan Bromley
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Compilation error
  • YesMann
Replies
2
Views
1K
YesMann
Y
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technology help
  • Matt North
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0
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1K
Matt North
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GHDL for VHDL simulation?
  • John Williams
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0
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2K
John Williams
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Patent granted for "system on a chip" framework?
  • y_p_w
Replies
9
Views
2K
y_p_w
Y
I
Error Generate Statement
  • Isaac
Replies
3
Views
3K
Keith Williams
K
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sync on multiple clocks
  • Spur
Replies
2
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5K
Mike Treseler
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DesignCon 2004 Call for Papers
  • J. Bhasker
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0
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2K
J. Bhasker
J
A
Comparison of Bit Vectors in a Conditional Signal Assignment Statement
  • Anand P Paralkar
Replies
2
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11K
Srinivasan Venkataramanan
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opencores.org - Question on project licensing?
  • Pacbell User
Replies
6
Views
2K
Jon Masters
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Frequency generation
  • YesMann
Replies
1
Views
2K
Charles M. Elias
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VHDL Simulation for Linux
  • Neil Zanella
Replies
2
Views
21K
=?ISO-8859-1?Q?Uwe_Klo=DF?=
?
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Book on VHDL.
  • Roberto Gallo
Replies
1
Views
5K
Ajeetha Kumari
A
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Re: Multi Cycle path and False paths
  • Subroto Datta
Replies
9
Views
26K
Nicholas C. Weaver
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where to find DCT/IDCT for JPEG/JPEG2000 VHDL/VERILOG source code?
  • walala
Replies
0
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11K
walala
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tool to draw FSM bubble diagram
  • Ingmar Seifert
Replies
5
Views
26K
Pedro Claro
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Question: String matching with CAM?
  • Seth
Replies
1
Views
2K
Ray Andraka
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Re: binary to BCD assistance
  • Glen Herrmannsfeldt
Replies
4
Views
8K
FE
F
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Downloading into XCV600
  • Isaac
Replies
0
Views
1K
Isaac
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Xilinx FPGA protoboard < $200
  • Mark Riegert
Replies
1
Views
3K
Thomas Fuchs
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Which method is better ? (about mux)
  • Fano
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0
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2K
Fano
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TestBench problem for ROM table
  • rajan
Replies
1
Views
5K
Marcin
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the textio lib and std_logic_textio
  • Pedro Claro
Replies
3
Views
14K
Mike Treseler
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?
VHDL
  • =?ISO-8859-1?Q?Stein_Kj=F8lstad?=
Replies
2
Views
2K
Amontec Team
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GL85 synthesizable code
  • Saeed Nari
Replies
2
Views
2K
Antti Lukats
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writing cordic
  • Gnome
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0
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3K
Gnome
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type conversion and concatenation
  • Ralf Hildebrandt
Replies
3
Views
9K
MK
M
A
why registered output?
  • Alex
Replies
2
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15K
Chris Pruett
C
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Port mapping to (SIGNAL_NAME'range=>'0')?
  • Ken Morrow
Replies
2
Views
9K
Jerold Green
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Relative placement constraints in VHDL for Virtex multipliers
  • Jack Stone
Replies
1
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2K
Symon
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XST fails to recognize FSM with registered outputs
  • E. Backhus
Replies
2
Views
8K
Alain
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Altera to Xilinx
  • Ronny Hengst
Replies
1
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3K
Andras Tantos
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Help: conditional attribute assignment
  • itsme
Replies
1
Views
3K
Ralf Hildebrandt
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Sun Monitor
  • Thomas Reinemann
Replies
0
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2K
Thomas Reinemann
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J
Slow Synthesis
  • Jeremy Pyle
Replies
5
Views
2K
Jeremy Pyle
J

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