VHDL

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comp.lang.vhdl
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VHDL Binary Waveform
  • bturnbul
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2
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1K
joris
J
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count leading zeros
  • lucahtc
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0
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1K
lucahtc
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C
Problem reading binary chunks from file
  • ColdStart
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0
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1K
ColdStart
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How to Program a Xilinx Virtex II PRO XC2VP30
  • udayjayachandran
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0
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2K
udayjayachandran
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Problem in an ALU design
  • ashfaq2419
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1
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2K
joris
J
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Need help - VHDL CODE for my project
  • udayjayachandran
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3
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2K
jeppe
J
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constants of sfixed in architecture body
  • Paul
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5
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2K
Paul
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comprehensive documentation for writing testbenches in VHDL
  • Marcin Rodzik
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5
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2K
backhus
B
P
sfixed in generics
  • Paul
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1
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1K
Tricky
T
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how to implement CLZ (count leading zeros) behavioural, using only gates
  • lucahtc
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0
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2K
lucahtc
L
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Writing null into file
  • Przemys³aw Elias
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3
Views
882
KJ
K
F
Inout questions in testbench
  • faust861
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0
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1K
faust861
F
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how to restart pointer 'line'
  • heziro
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0
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914
heziro
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Can you take attributes from array type element?
  • Tricky
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2
Views
807
Andy Rushton
A
S
VHDL simulation problem
  • shahulakthar
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0
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1K
shahulakthar
S
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vhdl free simulator??
  • Maurice
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4
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2K
d_s_klein
D
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Altera DE2 - PC high speed connection
  • profeta64
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0
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1K
profeta64
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?
Energy Saving Tips
  • ..
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0
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1K
..
?
A
Components with GENERICs
  • Analog_Guy
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3
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3K
Analog_Guy
A
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interface DAC in VHDL
  • dptmt
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0
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2K
dptmt
D
E
need help in VHDL FIR filter very urgent
  • erick232
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3
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2K
erick232
E
C
Discrepancy between functional simulation and post-synthesissimulation when inferring a block-RAM
  • Cesar
Replies
7
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2K
Mike Treseler
M
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help
  • yoogy
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4
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1K
joris
J
E
need help in VHDL FIR filter
  • erick232
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0
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1K
erick232
E
B
Dummy question about bidiretional Bus
  • Bluette
Replies
1
Views
972
Bluette
B
N
VHDL connecting block different timing
  • niyander
Replies
1
Views
1K
KJ
K
A
Byte stuffing while getting constant bytes input
  • Abu Saliha
Replies
2
Views
2K
Abu Saliha
A
H
Using abstract generic
  • hssig
Replies
7
Views
912
Allan Herriman
A
F
Timing Simulation with Altera-Modelsim
  • faust861
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0
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2K
faust861
F
V
How to detect a sync and start of a frame in an optimal way
  • VIPS
Replies
6
Views
2K
Mike Treseler
M
J
Setting up a tri state buffer in VHDL with 2 clks
  • jacqueskleynhans
Replies
1
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3K
jeppe
J
K
breakpoint in post route simulation...
  • kodadimet
Replies
0
Views
991
kodadimet
K
L
Unconstrained array: How would this component be described
  • Lars
Replies
5
Views
3K
Andy
A
X
Dynamically accessing a vector
  • XRay123
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0
Views
743
XRay123
X
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Making a timer out of TFFs
  • laserbeak43
Replies
12
Views
2K
KJ
K
D
Basic file read access using VHDL
  • Derdonn
Replies
2
Views
1K
Derdonn
D
J
variable : Integer to STD_logic conversion in Altera
  • Joseph
Replies
2
Views
2K
Tricky
T
M
USB 3.0 implementation on FPGA
  • Maurice Branson
Replies
10
Views
11K
edb_123
E
T
MIG(3.4) + Virtex(6) Clocking?
  • TheProperNoun
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0
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2K
TheProperNoun
T
3
VHDL Quesiton
  • 3bdallah
Replies
4
Views
1K
joris
J
I
synthesis of exit in for loop
  • ikbangesh
Replies
1
Views
1K
eliascm
E
W
Fun with interfacing GHDL
  • whygee
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0
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1K
whygee
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M
Cross Clock Domain Control
  • M. Norton
Replies
8
Views
2K
Andy
A
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VHDL newbie --VGA--PS2--calculator
  • viper987
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0
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2K
viper987
V
M
A challenging opportunity for Linux kernel Developers.
  • Mary
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0
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1K
Mary
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converting a subtype to unsigned?
  • laserbeak43
Replies
3
Views
1K
laserbeak43
L
F
VHDL model of a RS 232 transmitter
  • fpgawizz
Replies
14
Views
27K
lenux56
L
L
D flip flop setup and hold timings.
  • luvdhams23
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0
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2K
luvdhams23
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B
Need help figuring out how to control this.. edge triggering.
  • BlackHelicopter
Replies
1
Views
1K
eliascm
E
S
Graphical User Interface project on Spartan-3 FPGA
  • Simon Piekert
Replies
5
Views
5K
backhus
B

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