VHDL

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comp.lang.vhdl
M
Generating JEDEC for GAL programming?
  • Merciadri Luca
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3
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5K
Maurice
M
F
[PROBLEM]BLOCK RAM inferencing failed
  • fantomass
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0
Views
1K
fantomass
F
M
Are there any differences between 'Synplicity VHDL compiler, v1.0, b. 074R' and GHDL compiler?
  • Merciadri Luca
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5
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2K
Merciadri Luca
M
H
replace with sums and shifs
  • Hyuma
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0
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1K
Hyuma
H
K
Initialize memory
  • kmponis
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0
Views
974
kmponis
K
K
Why is this code persnickety?
  • KK6GM
Replies
7
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1K
KK6GM
K
W
Reset Logic Function
  • We Ech Dee Ell
Replies
1
Views
1K
backhus
B
N
ANN: Multi-port register-file (memory) generator
  • Nikolaos Kavvadias
Replies
1
Views
1K
Leon
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Reset Logic Function
  • We Ech Dee Ell
Replies
0
Views
898
We Ech Dee Ell
W
Z
Can you give some idea about the question?
  • zidong
Replies
4
Views
1K
backhus
B
J
VHDL Combinatorial + Sequential + Timing?
  • Jonathan Ross
Replies
0
Views
2K
Jonathan Ross
J
S
DCM Doubling
  • ShortCircuit
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0
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2K
ShortCircuit
S
H
VHDL2008 & Modelsim
  • HT-Lab
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1
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2K
Matthias Alles
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M
Help! VHDL analysis on quartus II won't work, 3 errors
  • mangoflango
Replies
1
Views
1K
joris
J
M
Problem viewing waveforms using gtkwave
  • mohitdaksh
Replies
4
Views
2K
mohitdaksh
M
E
Please help me in VHDL MuX or else my life is in danger
  • erick232
Replies
3
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2K
joris
J
K
Generate component
  • kmponis
Replies
3
Views
1K
joris
J
J
Job offer as Senior FPGA Engineer
  • Jaime Andres Aranguren C.
Replies
0
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1K
Jaime Andres Aranguren C.
J
H
Integer with leading zeros to string
  • hssig
Replies
7
Views
2K
Jonathan Bromley
J
J
Anyone help me please. VHDL code of simon game.
  • jumbo
Replies
0
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3K
jumbo
J
E
xst:737
  • elad1434
Replies
5
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4K
joris
J
X
VHDL process synthesis problem
  • xiheasas
Replies
2
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1K
xiheasas
X
C
Variables instead of signals: what about constraints?
  • Cesar
Replies
8
Views
2K
Pontus
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O
Start statemachine without clock
  • otis
Replies
2
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1K
otis
O
S
Available: Open Source VHDL parser - for free
  • Sumit Gupta
Replies
5
Views
8K
QuestaTechnologies
Q
T
Extracting type - Not possible or would it be useful in a future standard?
  • Tricky
Replies
4
Views
1K
JimLewis
J
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Latch inference when default is missing in case statement
  • We Ech Dee Ell
Replies
8
Views
3K
Andy
A
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Did VHDL-2008 get lost ?
  • hssig
Replies
15
Views
6K
Chris Higgs
C
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Java VHDL Parser
  • Bernhard Peischl
Replies
5
Views
8K
QuestaTechnologies
Q
S
Is my simulator on crack? (yes, it's Xilinx)
  • sketyro
Replies
2
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1K
sketyro
S
P
Xilinx fft core simulation
  • Parvathi c
Replies
0
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2K
Parvathi c
P
B
How to create a directory in VHDL Simulation
  • Benjamin Couillard
Replies
1
Views
3K
Jonathan Bromley
J
A
help in image processing....
  • alangs
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0
Views
982
alangs
A
A
problem whit program ycrcb to rgb
  • andrea90
Replies
0
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1K
andrea90
A
C
Noise Filter on Master Reset ?
  • Calvin C
Replies
5
Views
1K
KJ
K
C
Reading image file
  • chandrakant birajdar
Replies
2
Views
880
Paul Colin Gloster
P
V
ModelSim Question
  • vtc
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0
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5K
vtc
V
T
generic integer and hex notation
  • tonib
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0
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1K
tonib
T
N
Writing & reading same file
  • Niv (KP)
Replies
2
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1K
Jonathan Bromley
J
P
process with two clks in sensitivity list problem
  • pupillo
Replies
2
Views
1K
pupillo
P
M
call for Research Papers
  • managing editor
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0
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941
managing editor
M
M
Problem with bcd conversion
  • Manaryu
Replies
1
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2K
Manaryu
M
D
DDS
  • darkiller89
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0
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923
darkiller89
D
D
FIFO structure
  • darkiller89
Replies
0
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1K
darkiller89
D
P
Equivalent of SystemVerilog Interface in VHDL?
  • Poojan Wagh
Replies
4
Views
5K
JimLewis
J
D
CFP: EvoHOT 2011
  • Dr. Giovanni Squillero
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0
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1K
Dr. Giovanni Squillero
D
C
Simple state-machine problem (how to memoriza inside process)
  • Carlos
Replies
1
Views
1K
jeppe
J
T
Where did the Null array come from?
  • Tricky
Replies
9
Views
3K
Jonathan Bromley
J
B
gtkwave 3.3.8 is available, note on OS X
  • bybell
Replies
6
Views
2K
bybell
B
S
Signed operation in VHDL
  • sridar
Replies
0
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1K
sridar
S

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