VHDL

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comp.lang.vhdl
S
Do you have a separate Verification team?
  • Swapnajit
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0
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887
Swapnajit
S
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search for netnames in design analyzer
  • Thomas Gutzler
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1
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931
davidjaffer666
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Testbench with clock issue
  • Kyle H.
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8
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10K
shyam.krishnan.r20
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Node contains cycle
  • TwentyFlight
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0
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1K
TwentyFlight
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Re: How to use easics crc generator?
  • Jan Decaluwe
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11
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11K
OutputLogic
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C
Help with VHDL
  • Centurion210
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0
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2K
Centurion210
C
C
Problem to compile vhdl code
  • Cell
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4
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2K
Cell
C
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Launch ModelSim shell file
  • wolfy_
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1
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2K
wolfy_
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Detection of two rising edges
  • Dileptor
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2K
Dileptor
D
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generics in vhdl
  • nachzeher
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7
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39K
mink
M
H
Delaying signal assignment
  • hssig
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4
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1K
hssig
H
M
Procedures and Registers
  • makeuptest
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3
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1K
Mike Treseler
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Internal Prak Ramp Module
  • RicardoNeves
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0
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1K
RicardoNeves
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fpga board with parallel dac?
  • picnanard
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1K
picnanard
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Error in Verilog - Calling Other Files in Same Project
  • Testing Test
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0
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Testing Test
T
E
vhdl procedure question
  • eddiewonder
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1
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2K
joris
J
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Problem with Verilog Code - Simulation Not Stopping
  • Testing Test
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0
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1K
Testing Test
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Buzzer
  • Merciadri Luca
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3
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2K
Merciadri Luca
M
M
Pin numbers assignment
  • Merciadri Luca
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4
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6K
Merciadri Luca
M
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boolean operations on "integer" in VHDL'93
  • whygee
2
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31
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7K
Colin Paul Gloster
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Resume: Design Verification Consultant (Specman)
  • Veritec
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1
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5K
valdonio
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J
XST - configuration - VHDL
  • Jaime Andrés Aranguren Cardona
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6
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3K
Jaime Andrés Aranguren Cardona
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J
Programmable Logic at StackExchange
  • Jonathan Ross
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1
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1K
saar drimer
S
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VHDL Beginner help
  • tulio21z
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1
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5K
jeppe
J
N
Custom views in ModelSim
  • Niv (KP)
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1
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1K
Jonathan Bromley
J
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VHDL Feature Suggestions
  • Jonathan Ross
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6
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2K
JimLewis
J
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matrix generation
  • Damian Drewulski
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1
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952
Tricky
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GECCO 2011: Call for Papers on Artificial Life, Robotics, EvolvableHardware Track
  • Dr. Giovanni Squillero
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0
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1K
Dr. Giovanni Squillero
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M
Quadruple assignment
  • Merciadri Luca
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7
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1K
rickman
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J
Display test on Active-VHDL
  • joao12345678joao
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2
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1K
joao12345678joao
J
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Element update within records
  • Matthias Alles
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6
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1K
Matthias Alles
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J
VHDL Study Group Meeting Notice
  • JimLewis
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0
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1K
JimLewis
J
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Generate statement with varying signal width
  • Matt Longbrake
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5
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2K
Jonathan Bromley
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Declaration hides port port_name / Port port_name hidden by declaration in architecture
  • Merciadri Luca
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2
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4K
Merciadri Luca
M
M
Two different `architecture' implementations?
  • Merciadri Luca
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4
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1K
Merciadri Luca
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A
Boracay Weather Forecast
  • April Andy
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0
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2K
April Andy
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Can one declare more than one signal on one line?
  • Merciadri Luca
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4
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2K
Andy
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Substitute for Flip-Flop
  • Manaryu
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0
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1K
Manaryu
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assert of generic, during synthesis
  • whygee
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7
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2K
whygee
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?
Fueling your car with natural gas from home
  • ......
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0
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......
?
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Black boxing direct instantiation
  • Tricky
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3
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1K
Andy
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entire 32 bit two's complement integer range is supported in VHDL?
  • c.d.b.meis
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0
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2K
c.d.b.meis
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std types
  • Nipo
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2
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1K
Andy
A
M
vhdl code for AES
  • manjunath.rg
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9
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7K
rishirockzful
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type casting / conversion again
  • Shannon
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10
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2K
Jonathan Bromley
J
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if generate causes conflicts
  • janeruth
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1
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1K
janeruth
J
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Me and Latches...
  • laserbeak43
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11
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2K
rickman
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J
If
  • janeruth
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0
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1K
janeruth
J
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Fixed Point Arithmetic
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0
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1K
[email protected]
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Help needed in Control Unit VHDL
  • DanielGoh
Replies
3
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3K
joris
J

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