VHDL

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comp.lang.vhdl
B
Advanced use of VHDL - Factorial example
  • Bert_Paris
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13
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7K
Nicholas Paul Collin Gloucester
N
C
Problems going from synthesis to routing
  • c64
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2
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913
JohnDuq
J
V
How to use the 'event in Xilinx?
  • VHDLstudent
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4
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1K
VHDLstudent
V
A
file missing error
  • aralimaradsir
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3
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741
LittleAlex
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C
Avoiding gated clocks for counters
  • c64
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1
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1K
jeppe
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Halt synthesiser with an assert?
  • Tricky
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14
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3K
Sean Durkin
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O
VHDL For-Loop Index .. can it be of discrete range ?
  • omara007
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0
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1K
omara007
O
R
Using Generics to Define Ranges
  • rickman
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4
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3K
rickman
R
E
VHDL finite state machine
  • ekelly30
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11
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9K
ekelly30
E
D
Extended draft paper submission: HPCNCS-09 call for papers
  • devipsrs
Replies
0
Views
878
devipsrs
D
O
Max. number of write ports in a register file
  • omara007
Replies
0
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799
omara007
O
D
Pythagoras Theory In VHDL
  • davefowler1987
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2
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1K
JohnDuq
J
S
simulating 8255
  • Shalini Keshavamurthy
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4
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1K
priyvrat5
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Signal Processing Using VHDL
  • tang
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8
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5K
ratrace
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Defining Stimulus type and encapsulating parameters
  • Tricky
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7
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1K
Andy
A
V
Register - count up and remember value
  • VHDLstudent
Replies
2
Views
772
VHDLstudent
V
A
64bit DIVDER
  • ali5060
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2
Views
1K
c64
C
M
Simple question about hexadecimal values
  • Massi
Replies
1
Views
843
JimLewis
J
R
clock divide by n (n is variable)
  • rnpatil
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4
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3K
surpriya.7
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S
plz ...Verilog-HDL an up/down BCD counter
  • SQU
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1
Views
3K
JohnDuq
J
N
Intro VHDL - Questions
  • nihilanth100
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0
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1K
nihilanth100
N
B
Factorial solution
  • Bert_Paris
Replies
9
Views
5K
JimLewis
J
P
numeric_std resize function
  • Peter
Replies
5
Views
45K
Peter
P
K
global records (xilinx isim)
  • Ken Cecka
Replies
3
Views
2K
JimLewis
J
A
any program can generate block diagrams?
  • Aiken
Replies
8
Views
3K
Petter Gustad
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S
VHDL assignment
  • shanawaz
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2
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3K
shanawaz
S
O
constants as of array of integers, for loops
  • octavsly
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0
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1K
octavsly
O
Z
std.textio.all procedure read
  • Zhane
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0
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1K
Zhane
Z
A
Can you have multiple architecture declarations tied to the sameentity?
  • Aldorus
Replies
5
Views
7K
Aldorus
A
A
error in simulation
  • aralimaradsir
Replies
1
Views
635
Tricky
T
C
Non-Standard IEEE type "integer" error
  • c64
Replies
0
Views
1K
c64
C
B
Multiple components driving a single bus
  • Benjamin Couillard
Replies
2
Views
927
Benjamin Couillard
B
M
problem with high speed data transfer
  • mingyuexin
Replies
3
Views
870
JohnDuq
J
M
VHDL Programming help
  • mbrook10
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0
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1K
mbrook10
M
J
clock synchronization and flip flops
  • john
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10
Views
2K
JohnDuq
J
A
"sync_fifo" with Almost flags
  • ALuPin
Replies
2
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723
ALuPin
A
T
More synthesis myths?
  • Tricky
2
Replies
26
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2K
JimLewis
J
K
Computing needs, here's free root account on Solaris10
  • Kartik_Vashishta
Replies
0
Views
822
Kartik_Vashishta
K
S
8 bit full adder 2's complement
  • salvador1985
Replies
4
Views
14K
salvador1985
S
E
VHDL project
  • eman hanoun
Replies
4
Views
3K
eman hanoun
E
M
Smart coding for big multiplexer
  • Massi
Replies
6
Views
4K
Andy
A
L
The VHDL coding question
  • LiamChang
Replies
1
Views
1K
JohnDuq
J
T
Generating C header files?
  • T
Replies
1
Views
842
HT-Lab
H
R
VITAL PACKAGE
  • RealInfo
Replies
3
Views
1K
RealInfo
R
D
Extended draft paper submission: HPCNCS-09 call for papers
  • devipsrs
Replies
0
Views
714
devipsrs
D
H
Single and Double Precision Floating Point Modeling
  • Hybr1dz
Replies
1
Views
1K
JohnDuq
J
S
A Simple Integrated Circuit Design with Factorial Calculation
  • serkany
Replies
6
Views
3K
JohnDuq
J
D
VHDL -> block diagram
  • dave.bryan
Replies
18
Views
20K
JohnDuq
J
S
assign constant to signal
  • supra
Replies
1
Views
1K
JohnDuq
J
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How to constraint the In&Outputs of an ADC in XILINX ISE 9.2 (Virtex4 LX 60)
  • olliH
Replies
1
Views
2K
JohnDuq
J

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