VHDL

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comp.lang.vhdl
Q
How to get most significant bits
  • qharz
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2
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1K
KJ
K
D
IO-Link Slave Device IP Core
  • debayan_p
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1
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2K
debayan_p
D
B
Please Help in understanding a VHDL syntax
  • buddy249
Replies
1
Views
973
debayan_p
D
A
Power up state
  • Alfonso Baz
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2
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1K
Alfonso Baz
A
C
Spartan 3an Rotary Encoder
  • CreeD_XIII
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0
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2K
CreeD_XIII
C
K
problem: unwanted latches inferred
  • kelvinyung
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2
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2K
kelvinyung
K
M
runtime arguments in VHDL (ala plusargs in Verilog)
  • Mark
Replies
3
Views
3K
Mark
M
S
set dont touch attribute in xilinx xst?
  • Serkan
Replies
2
Views
7K
Serkan
S
S
error when wirting for processor(ERROR:Xst:827)
  • suraj.jain
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0
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1K
suraj.jain
S
T
Open Drain
  • tancming
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1
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2K
tancming
T
S
how to average samples from adc?
  • samsom
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0
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2K
samsom
S
S
Four dimensional array
  • sridar
Replies
0
Views
802
sridar
S
S
Four dimensional array
  • sridar
Replies
0
Views
801
sridar
S
S
intermediate signal simulation
Replies
0
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1K
[email protected]
S
P
VHDL signed addition does not yield correct result
  • pap74
Replies
0
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1K
pap74
P
S
Want flag to keep value through all states
  • Shannon
Replies
6
Views
1K
Mike Treseler
M
P
Modelsim PE/Win in VirtualBox?
  • Petter Gustad
Replies
7
Views
3K
Petter Gustad
P
W
Do you know how aggressive the patent fighting between Xilinx andAltera is going?
  • Weng Tianxiang
Replies
6
Views
1K
Weng Tianxiang
W
B
Testbench design references
  • Benjamin Couillard
Replies
2
Views
927
Benjamin Couillard
B
J
Pulse counter verification in vhdl
  • JSreeniv
Replies
2
Views
2K
JimLewis
J
K
Signal assignment inside for loop
  • krkrkr
Replies
1
Views
938
debayan_p
D
W
About Altera patent application "Logic Cell Supporting Addition ofThree Binary Words"
  • Weng Tianxiang
Replies
17
Views
1K
Weng Tianxiang
W
R
Overloading "*" operator to use my entity in VHDL
  • rdineshk
Replies
0
Views
1K
rdineshk
R
J
Modelsim resulution info
  • JSreeniv
Replies
2
Views
746
Mike Treseler
M
K
For loop delay???
  • krkrkr
Replies
5
Views
1K
jeppe
J
Z
ModelSim do file hotkey
  • zsotya
Replies
0
Views
2K
zsotya
Z
R
Burning the VHDL code on Virtex II pro board
  • rishikesh.sahoo
Replies
0
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1K
rishikesh.sahoo
R
G
vhdl loopback
  • GracelessROB
Replies
2
Views
2K
GracelessROB
G
T
Do I have a race condition for clk33_div?
  • Tim Doyle
Replies
2
Views
935
Mike Treseler
M
S
resynthesizing netlist files
  • sridar
Replies
0
Views
684
sridar
S
V
Division in VHDL
  • vikramtheone
Replies
0
Views
1K
vikramtheone
V
M
VHDL Newline using write
  • mmishra
Replies
1
Views
6K
mmishra
M
M
case statement concatenation condition
  • Mark
Replies
1
Views
3K
Mark
M
T
Use of 'simple_name/instance/path attributes - are they any use?
  • Tricky
Replies
4
Views
888
Martin Thompson
M
T
So, they started synthesizing shared variables?
  • Tricky
Replies
18
Views
4K
HT-Lab
H
C
CRC8 post-routing problems
  • c64
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0
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2K
c64
C
V
Image Processing... need help
  • vikramtheone
Replies
0
Views
974
vikramtheone
V
A
Modelsim Library Problem
  • Ardni
Replies
6
Views
9K
JohnDuq
J
S
Good SystemC tutorials or books?
  • sd
Replies
4
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4K
pini
P
V
I2C SDA LINE
  • VIPS
Replies
5
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2K
Bert_Paris
B
B
Anyone can check if XST v11 has fixed this bug ?
  • Bert_Paris
Replies
4
Views
1K
Bert_Paris
B
L
HELP!a bug in testbench
  • laSiA
Replies
4
Views
2K
JohnDuq
J
A
False Path Definition
  • Ardni
Replies
0
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2K
Ardni
A
N
Function Generic
  • netmonster
Replies
0
Views
635
netmonster
N
M
Initializing array of vectors VHDL
  • mbrook10
Replies
1
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28K
ttg1003
T
E
Digital Clock Help
  • evolgrin
Replies
1
Views
1K
jeppe
J
V
use of genric keyword in vhdl
  • vipul
Replies
0
Views
779
vipul
V
V
Basics of VHDL. Whats happening here?
  • vikramtheone
Replies
1
Views
996
jeppe
J
S
Constraint File Error: vhdl_bl3_ram8d_1.vhd
  • Sarah Li
Replies
1
Views
977
Mike Treseler
M
H
A Complete Web Development Solution | Halwasiya Infosys
  • halwits23
Replies
0
Views
922
halwits23
H

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