VHDL

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comp.lang.vhdl
S
Encoder counter problem
  • samith
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1
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2K
jeppe
J
R
Multi-source
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1
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991
jeppe
J
B
Resource/operator sharing, good or not?
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0
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865
bettercs
B
R
Using carry chain of counters for term count detect
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9
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1K
Andy
A
D
Entity Generics Question
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0
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673
dohzer
D
B
Real Random Number Generator
  • BarNash
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3
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2K
Symon
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J
vhdl code for Manchester
  • JSreeniv
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0
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2K
JSreeniv
J
J
Array of bits on to a signal in VHDL
  • JSreeniv
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4
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2K
JSreeniv
J
J
Manchester representation
  • JSreeniv
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0
Views
886
JSreeniv
J
J
serial stream data to capture in parallel line
  • JSreeniv
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3
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2K
backhus
B
J
Loops for write access
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3
Views
667
Andy
A
S
IP Core Wizard-Demystified
  • sridar
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0
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851
sridar
S
P
how 2 write vhdl for dsp applications
  • pravin.vhdl
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0
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1K
pravin.vhdl
P
J
VHDL Testbench representation
  • JSreeniv
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2
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2K
KJ
K
P
what is difference between generate and for loop in vhdl
  • pravin.vhdl
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0
Views
4K
pravin.vhdl
P
M
how to do a 1 to 4 demultiplexer in vhdl?
  • MNQ
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2
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13K
pravin.vhdl
P
E
A few VHDL questions
  • eksk86
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3
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1K
pravin.vhdl
P
F
VHDL record synthesis
  • Flo
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9
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4K
pravin.vhdl
P
T
new version TimingAnalyzer
  • timinganalyzer
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0
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869
timinganalyzer
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C
Nonlinear Time Scale ModelSim
  • c64
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0
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1K
c64
C
T
Connecting an inout port to another inout port
  • THurkmans
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14
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7K
Mike Treseler
M
S
Array assignment
  • sridar
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0
Views
821
sridar
S
V
FPGA-Camp - A mini conference on FPGAs, (Aug'26, Silicon Valley)
  • Vikram
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0
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1K
Vikram
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R
Using OPEN in port map
  • rickman
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13
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8K
KJ
K
S
The HDL Complexity Tool beta testing.
  • SladeMaurer
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0
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1K
SladeMaurer
S
D
Help with frequency divider
  • DaMeN
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2
Views
1K
i3igAnt
I
C
Reading a Vector to Create 5/9 Smoother
  • ctennant
Replies
1
Views
722
ctennant
C
B
gtkwave-3.2.2 released
  • bybell
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0
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1K
bybell
B
B
EVERAGE
  • BarNash
Replies
2
Views
855
Paul Uiterlinden
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D
Synplify - Init Rom from file - Howto?
  • dkbauter
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1
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4K
dkbauter
D
F
Reading 16 bit words from a file
  • Fredxx
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6
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4K
Fredxx
F
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Why cant protected types be elements in an array?
  • Tricky
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3
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2K
Tricky
T
E
VHDL code in Latex
  • Enes Erdin
Replies
6
Views
13K
Petter Gustad
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P
HELP! Searching for research participants
  • peter pawlicki
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0
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812
peter pawlicki
P
V
AM 2901 VHDL microprocessor slice
  • Vladutzz
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0
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2K
Vladutzz
V
J
Syntheis report??
  • Julia_10
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0
Views
864
Julia_10
J
N
Implementation of Register File VHDL Model
  • New User ^_^
Replies
3
Views
28K
sammy
S
A
Xilinx BRAM initialization with .coe file
  • aziz
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0
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3K
aziz
A
B
Xilinx BRAM initialization
  • Brad Smallridge
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5
Views
9K
aziz
A
A
read from a file
  • axr0284
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2
Views
4K
JimLewis
J
M
How to make Unconstrained std_logic_vector port :)
  • mido_nour1
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2
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2K
mido_nour1
M
S
8bit register with ALU computation
  • stts
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0
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2K
stts
S
R
Multiplication of 1 bit with vector
  • Renu
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2
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929
Renu
R
S
Stumped in Simulation Land
  • Shannon
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3
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934
Shannon
S
A
VHDL process and function problem
  • alomar
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6
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3K
Andy
A
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signal assignment and Delta delay
  • Roya
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4
Views
3K
Roya
R
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Is there a way to extract vhdl code from an fpga?
  • scottpops
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1
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3K
allsey_1987
A
M
Difference between two process
  • Mad I.D.
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4
Views
2K
Mad I.D.
M
H
Altera VS Xilinx
  • hayaloo
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0
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2K
hayaloo
H
M
Extracting digits [0-9] from an number/integer
  • --mms
Replies
7
Views
9K
Mike Treseler
M

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