VHDL

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comp.lang.vhdl
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c(0) <= a(0) + a(1); Found 0 definitions for operator "+"
  • matchstick86
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4K
matchstick86
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Why use DSP builder over HDL?
  • Tricky
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8
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3K
Andy
A
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Parity Check
  • Ed
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18
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13K
yassen
Y
A
ModelSim vs Aldec -- odd difference
  • Andy Peters
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9
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3K
Andy Peters
A
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Synplicity tool
  • sridar
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0
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897
sridar
S
P
using multiple ranges
  • paulk
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0
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866
paulk
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A
2's compliment+parity+parallel to serial help please...
  • axeman0226
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0
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1K
axeman0226
A
C
Please recommand a VHDL book for synthesis purpose
  • chanson
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2
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1K
chanson
C
J
Signals too slow
  • jcafaro10
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0
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855
jcafaro10
J
D
vhdl: wrong index type
  • dancar
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1
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3K
joris
J
D
3x3 sobel edge detection
  • dashdingo
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3
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9K
minhhn0205
M
S
Checksum comparisons
  • Shannon
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16
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2K
KJ
K
J
How to implement a counter
  • jcafaro10
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0
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2K
jcafaro10
J
V
Generic Multiplexer
  • Vinny P
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3
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5K
Vinny P
V
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clock divider quetion
  • tia86
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1
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1K
debayan_p
D
S
Verification Question
  • Shannon
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6
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919
Kenn Heinrich
K
N
how to implement this c++ algorithm in vhdl
  • niyander
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2
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2K
Mark McDougall
M
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Instantiating VHDL/Verilog modules (Generating the top level) usingan XML configuration file
  • turituri
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1
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3K
HT-Lab
H
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Stopping the simulation in Modelsim Altera Starter Edition/Linux?
  • Petter Gustad
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1
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2K
Petter Gustad
P
A
Testbench for geting currect time in ModelSim
  • Aiken
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1
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3K
KJ
K
A
log2(N)
  • ALuPin
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4
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21K
texvnirap
T
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linking readable port names with indexed array
  • mdearman
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0
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1K
mdearman
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M
std_logic_vector to string in hex format
  • Mad I.D.
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6
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7K
JimLewis
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Nike Shox Sneakers
  • wendy
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0
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3K
wendy
W
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Newbie VHDL Blocks
  • nvd
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2
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1K
debayan_p
D
F
Writing a binary output file
  • Fredxx
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9
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9K
Fredxx
F
N
state machine help
  • niyander
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1
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916
Andy
A
W
Does ModelSim or any simulator software have a function similar tothe standard function any logic an
  • Weng Tianxiang
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7
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2K
Paul Uiterlinden
P
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How many bits?
  • Tricky
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1
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1K
Marty Ryba
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B
xilinx warning message
  • Bstark
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0
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837
Bstark
B
S
ieee.math_real-support in Synplify for Lattice
  • Sean Durkin
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2
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2K
Sean Durkin
S
S
clocked for loop with conditional if...
  • shift_1_11
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0
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1K
shift_1_11
S
T
Pointer clarification needed
  • Tricky
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3
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999
Tricky
T
H
Mac OS X support for Sigasi HDT
  • Hendrik
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1
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1K
Andy Peters
A
P
How To Write Vhdl For Stepper Motor
  • pravin.vhdl
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0
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2K
pravin.vhdl
P
S
Help in VHDL for Test becnh signal generation
  • sdon
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1
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1K
thecolororange
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D
OT: Verizon will drop ALL newsgroups on 30 September
  • Dave Pollum
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1
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914
Mike Treseler
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D
Suggestion for Frame Handler Design
  • debayan_p
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1
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897
debayan_p
D
J
SPI, I2C and CPLD
  • john
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1
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3K
Rich Webb
R
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Assigning entire row in a 2d array?
  • Tricky
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2
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2K
Tricky
T
P
Bus Emulation in Testbenches
  • PeterHawk
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0
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1K
PeterHawk
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C
Accumulator type DCO
  • cherishnguyen
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1
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2K
eliascm
E
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Post-Synthesis simulation runs into iteration limit
  • THurkmans
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2
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2K
Tricky
T
T
record of a record to std_logic_vector
  • THurkmans
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2
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2K
KJ
K
F
Why there is multi-source error?
  • fl
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2
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3K
h.e.
H
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CFP - Journal of Systems Architecture, Embedded Software Design(Elsevier), Special Issue on Hardware
  • Juan A. Gomez-Pulido
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0
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3K
Juan A. Gomez-Pulido
J
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a small clarification please
  • naren
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2
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1K
debayan_p
D
J
how to pass input values to procedure
  • JSreeniv
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1
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1K
Tricky
T
F
coding style for arithmetic operations
  • Frank Buss
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2
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2K
Andy
A
B
Template for programming devices
Replies
0
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901
[email protected]
B

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