VHDL

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comp.lang.vhdl
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testbench question
  • Shannon
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6
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Shannon
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ieee.numeric_std?
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2
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10K
janeruth
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CPLD Algorithm
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2
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Marty Ryba
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Fir Question
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4
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700
BarNash
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Back to the future
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19
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Mike Treseler
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Synthesis VS Simulation
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834
hayaloo
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Do you prefer paper or plastic... er, I mean paper or e-books?
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9
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Colin Paul Gloster
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Provider of EDA tool licensing and MPW services in Singapore
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725
YMYip
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xilinx bram not connected?
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1
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2K
steve
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Some support for VHDL project
  • borissofia
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1
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1K
borissofia
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HELP required floating point multiplier on FPGA
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0
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1K
Nauman Mir
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Can I include include a constant in a constant array?
  • Fredxx
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3
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1K
Martin Thompson
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latch problem
  • kushan_2001
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2
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915
jeppe
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Constants?
  • Alfonso Baz
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4
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1K
Andy
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Why self defined type signal cannot assign value multiple times?
  • fl
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3
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3K
Thomas Stanka
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How to import data from matlab in to VHDL design
  • mailmekaran
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3
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7K
nanu
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std_logic_textio library
  • Shannon
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1
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2K
JimLewis
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Interpolation in VHDL
  • scottpops
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0
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scottpops
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syncronizer
  • Michael Thomsen
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2
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Michael Thomsen
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plz help me ,, i need some codes ,,plz enter
  • nocturnal
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1
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1K
nocturnal
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issue with Chipscope
  • steve
2
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20
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2K
Andy Peters
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How can I access a 2d array completely.
  • bharat1986
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1
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822
joris
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modelsim doesn't like my increment w/wraparound
  • Ben Voigt
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8
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2K
Andy
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Breaking parallel multiplier into two pieces in VHDL?
  • pap74
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0
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2K
pap74
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Dual_port_BRAM
  • steve
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0
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820
steve
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assigning different elements of array
  • Hemang
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5
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1K
Hemang
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TimingAnalyzer is now freeware
  • timinganalyzer
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5
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2K
Petrov
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FPGA / CPLD Group on LinkedIn -- Networking Group
  • cpld-fpga-asic
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13
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2K
rickman
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VHDL and Spartan 3E
  • Amit
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3
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2K
steve
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Delay counters in three process state machines
  • thecolororange
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1
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1K
cheevu
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Adding signals of different size
  • abidbodal
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2
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5K
abidbodal
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Simulating Inverted Registers
  • Shannon
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4
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1K
Thomas Stanka
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BAUD rate problem
  • debayan_p
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0
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1K
debayan_p
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Edge Detection circuit.
  • Raghavendra
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17
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36K
digitalpbk
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BCH(256,16,113) code
  • Niv (KP)
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3
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2K
Symon
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NEXYS2 Board from Digilent
  • mmishra
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0
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2K
mmishra
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I've got a case of the latches....
  • Shannon
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3
Views
857
Mike Treseler
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Expand unsigned 4*4 module to signed 16*16 module
  • Weng Tianxiang
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4
Views
744
rickman
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Need help initializing LPM_Add_Sub to do Sub
  • hellbinder
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0
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1K
hellbinder
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enum as array index
  • Shannon
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6
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1K
KJ
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pre-initialized dpram functional simulation
  • Serkan
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9
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1K
Mike Treseler
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Code Coverage in ModelSim
  • Matthias Alles
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13
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13K
NigelE
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Bootloader Problem
  • internet
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0
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900
internet
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Variable Length Generics, so close and yet so far
  • Lozaketh
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0
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1K
Lozaketh
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Help
  • jpaulobenevides
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0
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820
jpaulobenevides
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Help Please
  • jpaulobenevides
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0
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692
jpaulobenevides
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conversion variable to std_logic
  • Dr. Thomas Ansorg
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1
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1K
Andy
A
A
importing data in a test bensh?
  • alexglvr
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0
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694
alexglvr
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Gold code generator
  • Dimcliff
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5
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8K
nocturnal
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Call For Participation: WORLDCOMP'09 (The 2009 World Congress inComputer Science, Computer Engineer
  • A. M. G. Solo
Replies
0
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1K
A. M. G. Solo
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