VHDL

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comp.lang.vhdl
D
Tesbench loop (Run through all address/data line combinations)
  • Daryl
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0
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959
Daryl
D
I
Gizmo invent Gizmo. The State of the Art in 1999, today and thefuture. submitted by Mr Ian Martin Aj
  • iajzenszmi
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2
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1K
Mel
M
J
Top level output keeps showing undefined XXX in simulation
  • Jaco Naude
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5
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4K
Mike Treseler
M
A
How to perform a timing simulation in Modelsim with QuartusII output file ?
  • ALuPin
Replies
13
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10K
mouna
M
S
basic vhdl queries
  • sundar
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5
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1K
KJ
K
S
to_stdlogicvector ERROR
  • sebs
Replies
6
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2K
loris
L
J
Problem with post-route simulation / timing simulation
  • jasperng
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0
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2K
jasperng
J
F
Index Array (Yet Another Question)
  • Filipa
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0
Views
899
Filipa
F
D
Verilog's integer and reg?
  • Davy
Replies
5
Views
46K
partha
P
B
Can VHDL be implemented JTAG TAP controller?
  • Bruce Sam
Replies
9
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6K
reneske
R
P
Generation of 4.096MHz clock from 7.680MHz clock
  • pankaj.goel
Replies
6
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2K
pankaj.goel
P
S
color bars on vga monitor -VHDL
  • stanyeboah
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0
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3K
stanyeboah
S
P
Writing std_logic_vector?
  • Philipp
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4
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5K
Tricky
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M
data types and arithmetic ops
  • mkr
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5
Views
1K
pankaj.goel
P
A
Call for Papers: The 2009 World Congress in Computer Science,Computer Engineering, and Applied Comp
  • A. M. G. Solo
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0
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1K
A. M. G. Solo
A
M
others and unconstrained array
  • MariuszK
Replies
5
Views
4K
MariuszK
M
D
VHDL VGA controller
  • dashdingo
Replies
3
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20K
jpk216
J
S
Clock Frequency & timming constraints
  • samehsh
Replies
1
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1K
jeppe
J
M
VHDL Implementation of AES in WiMax Networks
  • mahshid29_elec
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0
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1K
mahshid29_elec
M
M
ISE v9 VHDL compilation
  • Mark McDougall
Replies
4
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1K
Allan Herriman
A
V
how to display on LCD of FPGA board?
  • vx100miles
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1
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3K
vx100miles
V
W
test bench
  • whereismelvin
Replies
1
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1K
Tricky
T
A
vhdl code generators ( crossposted in comp.hardware.fpga)
  • abe
Replies
1
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1K
Tricky
T
E
Complex testbench design strategy
  • Eli Bendersky
Replies
15
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2K
Mike Treseler
M
P
DOWNTO versus TO keyword on Component instantiation
  • pierre0102
Replies
1
Views
5K
jeppe
J
D
using both rising edge and falling edge of signal
  • denish
Replies
5
Views
9K
Andy
A
C
shift register
  • coderyogi
Replies
7
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6K
Mike Treseler
M
D
FOR LOOP in VHDL testbench?
  • Daryl
Replies
0
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5K
Daryl
D
C
Link for Joining the FPGA/CPLD Design Group on LinkedIn
  • cpld-fpga-asic
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0
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1K
cpld-fpga-asic
C
T
How portable is this code?
  • Tricky
Replies
2
Views
815
Martin Thompson
M
W
testbench
  • whereismelvin
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1
Views
1K
Tricky
T
M
Need help with LAB assignment
  • marksauder
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0
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1K
marksauder
M
A
most significant and less significant address
  • a01lida
Replies
2
Views
1K
a01lida
A
G
std_logic_vector'("0011100001111111") ??
  • guylewis
Replies
3
Views
815
jeppe
J
G
Signal Conditional Assignment ?
  • guylewis
Replies
0
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1K
guylewis
G
A
near LIBRARY :Syntax error
  • AnandA
Replies
1
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2K
Mike Treseler
M
A
Simple ALU Implementation
  • andrezz
Replies
3
Views
3K
andrew_ross
A
C
Signal Generator code
  • coderyogi
Replies
1
Views
3K
kennheinrich
K
A
Using Components in Processes
  • andrezz
Replies
1
Views
680
Dave
D
A
Simple ALU Implementation
  • andrew_ross
Replies
0
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1K
andrew_ross
A
N
select file soorce/destination at simulation start
  • Niv (KP)
Replies
2
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700
jtw
J
A
Coding style to improve timing
  • Ardni
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0
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769
Ardni
A
A
"Value of index is not static"
  • andrezz
Replies
4
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2K
andrezz
A
M
How to define a constant of an array of records?
  • mamu
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3
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2K
mamu
M
M
ISE 9.2.03i problem
  • Mark McDougall
2
Replies
21
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3K
Mark McDougall
M
U
floatfixlib synthesis
  • universeee
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0
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2K
universeee
U
W
output TY = = -1.#INF ???
  • wales_1986
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0
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680
wales_1986
W
L
Adc
  • lucianofalbo
Replies
7
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2K
lucianofalbo
L
T
request: sample vcd files for TimingAnalyzer
  • timinganalyzer
Replies
4
Views
2K
timinganalyzer
T
W
Design FIR filter in VHDL
  • wales_1986
Replies
0
Views
1K
wales_1986
W

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