VHDL

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comp.lang.vhdl
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ASIC to FPGA porting/migrating
  • sundar
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6
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sundar
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Moore State Change
  • knight
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3
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Dave
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ARM AMBA Designer licensing cost
  • guestuser1
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4
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Marcus Harnisch
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Compiling Error : "Value of index is not static"
  • andrew_ross
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2
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andrew_ross
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synthesizing problem about complex numbers
  • universeee
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0
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781
universeee
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PS/2 keyboard
  • Jowkar
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1
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1K
Jowkar
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Design Question..
  • hellerstvn
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809
Mike Treseler
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7 segment display
  • electronsteve
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0
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2K
electronsteve
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Avoiding metastability on asynchronous inputs
  • Ardni
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0
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1K
Ardni
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Unsigned subtraction
  • andrew_ross
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2
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3K
andrew_ross
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DDC and NCO
  • lucianofalbo
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2
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2K
sridar
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design of 2-bit adder in tree format
  • shan
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0
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shan
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Emacs VHDL-mode Compiler Setup
  • M. Norton
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2
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2K
Mike Treseler
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vhdl vector subtraction
  • nicx82
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4
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5K
jeppe
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the "|" operator
  • abasili
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6
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926
Mike Treseler
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Question about signals
  • Ardni
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4
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960
jeppe
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Route-Through
  • sridar
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0
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769
sridar
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Correct way of writing a mux followed by a register
  • Chris Maryan
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14
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2K
Chris Maryan
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about xilinx synthesizer.
  • Amit
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3
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1K
Enes Erdin
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needs help on CLOCK
  • vx100miles
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2
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953
vx100miles
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How IP cores are written
  • sridar
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0
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814
sridar
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HPCNCS-09 call for papers
  • john
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0
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852
john
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RS-232 Receiver and Transmitter Design in VHDL
  • jasperng
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0
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2K
jasperng
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Are there any Modelsim hooks to allow testbench code to figure out procedure call stack?
  • Andrew FPGA
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7
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2K
stephenmm
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LRM question: What is the correct interpretation of an inout signalwith a default value that is lef
  • KJ
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2
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1K
KJ
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vcd file generation in ncverilog tool
  • skishor
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0
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3K
skishor
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compiling from 3 party editor
  • Jan
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2
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684
Mike Treseler
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ncshell for creating vhdl packages from verilo
  • Andy Luotto
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1
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1K
Andy Luotto
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TimingAnalyzer beta version 0.90 -- beta testers wanted
  • timinganalyzer
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3
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1K
Pierre-François \(f5bqp_pfm\)
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Constants and signals in procedures
  • Chris P
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2
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1K
KJ
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Timing Question
  • Ardni
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0
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900
Ardni
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how to program virtex 4?
  • vx100miles
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4
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1K
vx100miles
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Connection to global signals
  • Tricky
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1
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926
Mike Treseler
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vMAGIC 0.1.1 (alpha) released
  • Jens Hagemeyer
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0
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889
Jens Hagemeyer
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example ucf file required
  • vx100miles
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0
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1K
vx100miles
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(8-bit binary to two digit bcd) or (8-bit binary to two digit seven segment)
  • Fangs
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3
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12K
darshana
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Altera Quartus II VHDL code compilation process
  • ssylee
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1
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2K
Mike Treseler
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Comparator- something wrong
  • sridar
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1
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837
jeppe
J
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Interesting EDK error !!!
  • knight
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2
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1K
knight
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Coding State Machines
  • Ardni
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6
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2K
Ardni
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PG Diploma in VLSI Design using FPGA- new batch strating from 4th Dec08
  • VLSI Training
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1
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1K
LittleAlex
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ISQED09 Final Call for Papers
  • ISQED
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0
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993
ISQED
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Help....16 bit I/O on sprtan 3e
  • robinsur
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0
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846
robinsur
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How to write system verilog testbench assertions for a VHDL design
  • zj82119
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0
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3K
zj82119
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Use of std_logic '-' don't care.
  • M. Norton
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5
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M. Norton
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Are constants not locally static?
  • M. Norton
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4
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3K
M. Norton
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Byte lane select
  • Jan
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4
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3K
KJ
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unsupported Clock statement. error message
  • Amit
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7
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3K
Andy
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Multiplication
  • sridar
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1
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1K
jeppe
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how to read jpg file using VHDL
  • raj
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10
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5K
Tricky
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