VHDL

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comp.lang.vhdl
M
Basic question #4
  • m
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10
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1K
KJ
K
M
Basic question #3
  • m
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5
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849
Tricky
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A
State Machine with single cycle pulsed outputs?
  • Analog_Guy
2
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24
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3K
m
M
T
Speech recognition
  • tang
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0
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989
tang
T
M
Basic question #2
  • m
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10
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2K
M. Norton
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M
Basic question
  • m
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6
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852
Svenn Are Bjerkem
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package containing a global signal and a proc whic modifies it
  • Ken Cecka
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4
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1K
Mike Treseler
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Truncate with fixed_pkg
  • Alfreeeeed
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4
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3K
Alfreeeeed
A
J
Emacs, vhdl, Windows XP, some problems
  • jerzy.gbur
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2
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1K
Mike Treseler
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B
VHDL NAND flash model
  • beckjer
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1
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5K
Rick
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A
reading strings with different lengths
  • ALuPin
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5
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832
Guest
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R
help~!
  • red
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0
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827
red
R
S
Can port Maps be expressions?
  • Shannon
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2
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783
Andy
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M
Generic Component Instantiation
  • minhajhassan
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0
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1K
minhajhassan
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M
Structured Verification Request for Information
  • M. Norton
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10
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2K
Marcus Harnisch
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S
2 Queries please
  • SarmadEdward
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0
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912
SarmadEdward
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8bit Limit on Enumerated Type?
  • GuruSY
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1
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815
GuruSY
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S
a small vhdl problem
  • s_hlu
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1
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788
jeppe
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M
how to solve implantation design with 4leds and 3DIP switches
  • mitsui9999
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0
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960
mitsui9999
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A
How can i do combination logic in VHDL
  • Aiken
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2
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3K
Thomas Stanka
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G
frequency divider
  • Gandalf
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6
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29K
solrac215
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vhdl shifting command
  • red
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0
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3K
red
R
P
Need Help, please take look my VHDL code.
  • piapia
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0
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1K
piapia
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E
Data type used in VHDL
  • ecenus
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3
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2K
Steff
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Z
error in quadrature design
  • zes
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7
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1K
jeppe
J
F
problems using EMACS vhdl project
  • ferna_2008
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1
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2K
Aiken
A
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Strange synthesis result , getting crazy
  • raisul
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0
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763
raisul
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R
Port sin LUT from VHDL to Verilog
  • rthompso
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3
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4K
Kevin Neilson
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Fifo
  • ramzitligue
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1
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1K
Steff
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C
synopsys DC synthesis errors
  • chinski
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0
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1K
chinski
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Forum VHDL in Italiano
  • Bernasconi Sacha
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10
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7K
safaryway
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ISQED 2009 Call for Papers
  • ISQED
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0
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1K
ISQED
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Declaring array of length 1
  • Tricky
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4
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2K
KJ
K
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Ranking Modelsim Coverage results using Python for Speed? !
  • Paddy3118
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4
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2K
Paddy3118
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Clock sampling with unisim FDCPE (virtex5)
  • eko
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1
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2K
eko
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M
Fatal Error Modelsim Ok Xilinx
  • mreister
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5
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2K
Steff
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Infix operator "+" Error
  • wadia
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1
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4K
wadia
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simulation trouble
  • Vandana
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2
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724
Tricky
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VHDL ... What wrong with my real number???
  • elements_me
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1
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4K
Steff
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H
interface (cdd to DE2)
  • hsvjap
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0
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976
hsvjap
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Newbie Question
  • Tarique
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1
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789
KJ
K
S
Components in VHDL
  • samehsh
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0
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7K
samehsh
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M
Procedures-functions Vs Processes?
  • mreister
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1
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1K
jeppe
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A
issue converting of std_logic_vectors into integers
  • Andy Luotto
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1
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1K
KJ
K
H
divide by 3
  • hsvjap
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0
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939
hsvjap
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A
configurations and generics
  • Andy Luotto
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4
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1K
Andy
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How to put part of one array into another
  • none
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1
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958
KJ
K
A
Using SPI core in EDK 9.1
  • AlexQ
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0
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2K
AlexQ
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Legal enable?
  • PatC
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18
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1K
Andy
A
K
Signed multiplication
  • knight
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14
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10K
KJ
K

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