VHDL

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comp.lang.vhdl
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Fixed-point packages
  • k4kami
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0
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918
k4kami
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E
Europe's Best Computer Enthusiast Website, Eurotechzone is now Open!
  • Eurotechzone
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1
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694
TehPron
T
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synthesizing many modules
  • cosmonutt
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0
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668
cosmonutt
C
C
lpm rom
  • cLaRe
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0
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1K
cLaRe
C
P
Illegal concurrent statement?
  • Philipp
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4
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4K
Luc
L
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Xilinx - file io error for a small rom
  • tanukichu
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2
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2K
jeppe
J
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ANNOUNCE: TimingAnalyzer version beta 0.87
  • timinganalyzer
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17
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2K
rickman
R
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Modelsim : Problem with generics
  • XSterna
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14
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4K
XSterna
X
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help about conversion!
  • loris
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1
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802
jeppe
J
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Problems with Access types
  • Tricky
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1
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872
KJ
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Free Seminar on Advanced Verification with Aldec’s Riviera-Pro
  • cvc.training
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0
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1K
cvc.training
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"ack" is reserved keyword in VHDL?
  • rl
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2
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1K
kennheinrich
K
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Adding reference into a record type
  • Tricky
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4
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867
KJ
K
C
real input
  • cLaRe
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4
Views
755
cLaRe
C
M
variable in a loop
  • Matthias Alles
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7
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808
Thomas Stanka
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C
binary point
  • cLaRe
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0
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705
cLaRe
C
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help me !
  • mara
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0
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765
mara
M
E
Low cost solution to program Spartan 3AN DSP development boardAES-SPEEDWAY-S3ADSP-SK
  • Etantonio
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2
Views
917
Etantonio
E
C
Delaying vectors with an array
  • Cesar
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1
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912
Tricky
T
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VHDL example using Opencores I2C component
  • kimberlinbw
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0
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2K
kimberlinbw
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C
complex number
  • cLaRe
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0
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812
cLaRe
C
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ANNOUNCE: TimingAnalyzer version beta 0.86
  • timinganalyzer
Replies
3
Views
1K
timinganalyzer
T
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odd behaviour
  • andy
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12
Views
1K
rickman
R
C
conv_integer for unsigned value
  • Clemens
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9
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6K
rickman
R
O
range attribute on integer failure
  • Olaf
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3
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829
Andy
A
C
exponent in vhdl
  • cLaRe
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4
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2K
cLaRe
C
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see all hardware importent
  • pandu
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1
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731
rickman
R
B
What does the sharp sign mean in VHDL?
  • bigyellow
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5
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6K
diogratia
D
C
exponential in VHDL
  • cLaRe
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0
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3K
cLaRe
C
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Injecting glitch on bidirectional line
  • ALuPin
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4
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1K
KJ
K
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vhdl architecture configuration
  • mike_m
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0
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2K
mike_m
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Problem with TextIO
  • Rob Keiber
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7
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1K
Martin Thompson
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what design changes are required for speed improvement
  • kiranec2004
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1
Views
720
jeppe
J
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Difference between IEEE packages
  • Martin Sauer
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1
Views
861
flintstone
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A
Modelsim "Cannot read output"
  • Ardni
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3
Views
3K
Ardni
A
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mixing in and out in the declaration of a port
  • cvt
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0
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799
cvt
C
F
VHDL question (what is the better architecture for this design?)
  • flatiron
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8
Views
3K
Mike Treseler
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N
Spansion 29GL256P model
  • Niv (KP)
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0
Views
950
Niv (KP)
N
M
Sythesis vs. Simulation
  • Mike
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2
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669
Tricky
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I
wrong index type for array?
  • ieee.sucks.all
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0
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2K
ieee.sucks.all
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ncelab // synplify_pro // qu(at)rtus //
  • bossbebes
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0
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1K
bossbebes
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VHDL question about algorithm implementation
  • flatiron
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0
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1K
flatiron
F
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State machine going into unknown state
  • axr0284
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6
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2K
Mike Treseler
M
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Using an array value as indices for an array
  • KLaus Blank
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1
Views
867
Dave
D
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Free Webinars on PMP Certification Awareness and Roadmap
  • makarand
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0
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912
makarand
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A
ram
  • AMARO
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2
Views
990
Rick
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Round-robin priority encoder
  • Pasacco
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2
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2K
Mike Treseler
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using signals as registers and initialization
  • rehansherwani
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0
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796
rehansherwani
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T
ANNOUNCE: TimingAnalyzer version beta 0.85
  • timinganalyzer
Replies
9
Views
1K
rickman
R
K
flaw in to_signed() for big numbers?
  • Kevin Neilson
Replies
8
Views
3K
KJ
K

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