VHDL

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comp.lang.vhdl
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Maximum combinational path delay
  • samehsh
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0
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4K
samehsh
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A
any freeware can convert vhdl file to schematic(block diagram)?
  • Aiken
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2
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4K
Shannon
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How to calculate the clock period?
  • billys13
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3
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3K
jeppe
J
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ISE Simulator
  • samehsh
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0
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912
samehsh
S
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VHDL Operator associativity (Quartus II parser bug?)
  • Fons
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9
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2K
Fons
F
P
Initializing Single Row of 2-D Array
  • pessenm
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0
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758
pessenm
P
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simulation differences in modelsim
  • koyel.aphy
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6
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2K
koyel.aphy
K
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Problem while writing the file
  • Shraddhs
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0
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776
Shraddhs
S
F
VHDL Operator associativity (Quartus II VHDL parser bug?)
  • fons
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0
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1K
fons
F
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What's your design platform ?
  • whygee
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3
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899
whygee
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Cadence compiler basics
  • PC
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1
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3K
HT-Lab
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C
FPGA to solve the two most annoying problems on usenet - SuggestionsWelcome
  • Charles Xavier
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11
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1K
Arash Partow
A
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VHDL bidirectional buffer?
  • John5788
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1
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3K
jeppe
J
F
What is the best way to generate 6 set 3-bit address
  • fl
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2
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764
Andy
A
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What am I missing... again?
  • rickman
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2
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739
rickman
R
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SV assertions workshop in San Jose , 20th June
  • SVTII
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0
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745
SVTII
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N
Signed, Unsigned syntax issues. Please help, I'm stumped
  • nitrogenocide
2
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35
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4K
KJ
K
P
Populating Array In a Procedure
  • pessenm
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1
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1K
pessenm
P
O
How Initialize 2 block ram with xilinx project navigator
  • oskarathletic
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0
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1K
oskarathletic
O
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timing in ISE Simulator
  • samehsh
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0
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831
samehsh
S
O
become crorepati in less than one year by trading into indian stockmarket optiontrading.
  • optionmaster
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0
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804
optionmaster
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Bad synchronous description, how to fix it??
  • tarzandavid
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1
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2K
jeppe
J
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Now I'm pissed
  • rickman
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8
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1K
Patrick Dubois
P
K
Microblaze in System generator
  • klauspetersen
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0
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1K
klauspetersen
K
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ANNOUNCE: TimingAnalyzer -- new updated version
  • timinganalyzer
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3
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1K
rickman
R
F
Which version of VHDL supports delimited comments.
  • fl
Replies
3
Views
887
Tim McBrayer
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D
FPGA to FLASH and back?
  • Denkedran Joe
Replies
3
Views
851
Hauke D
H
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If statement with String condition
  • ROOZ
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4
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2K
ROOZ
R
M
Resincronization problem: slow to fast domain
  • mmarco76
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0
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767
mmarco76
M
H
How to "or" a generic array of std_logic_vector ?
  • HansWernerMarschke
Replies
6
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1K
KJ
K
B
Xemacs vhdl-mode editing header string
  • bluesforsalvador
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0
Views
662
bluesforsalvador
B
S
Test Vector for finite field
  • samehsh
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0
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699
samehsh
S
P
ASIC and FPGA : inferring multiplier
  • Pasacco
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8
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4K
Pasacco
P
B
Xemacs vhdl-mode.el editing/compiling question
  • bluesforsalvador
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0
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1K
bluesforsalvador
B
M
Advice in testing a simple RAM code.
  • mrnobody
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0
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1K
mrnobody
M
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Get the delay time
  • samehsh
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0
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732
samehsh
S
M
VHDL
  • mukhram443
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1
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881
Nicolas Matringe
N
O
Clock divider?
  • oppenheimer
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2
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2K
oppenheimer
O
S
FPGA Equations list (like cpld)
  • sonaj
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0
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873
sonaj
S
S
vector to integer
  • sonaj
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2
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796
sonaj
S
N
Modelsim6.2f with gcc 3.4.4-----for SystemC simulation
  • Neha
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4
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2K
Neha
N
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How to print the .ngr-files or the pictures from the ISE simulator ?
  • HansWernerMarschke
Replies
0
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925
HansWernerMarschke
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G
DMA Controller
  • gbanegas
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0
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2K
gbanegas
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ANNOUNCE:-- TimingAnalyzer Free Version -- Draw timing diagrams
  • timinganalyzer
Replies
15
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4K
Jack
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Multiple errors in VHDL
  • degrau3
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0
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1K
degrau3
D
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to_stdlogicvector and to_unsigned
  • seinal
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3
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21K
jeppe
J
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Defined ranges
  • rickman
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2
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824
rickman
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Hardware doesn't work!
  • oppenheimer
Replies
2
Views
803
jeppe
J
R
What Simulators support PSL?
  • Reuven
Replies
3
Views
919
NigelE
N
M
simple project suggestions
  • miss zia
Replies
5
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933
miss zia
M

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