VHDL

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comp.lang.vhdl
K
A constant with if-else-if
  • Kevin Neilson
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12
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4K
KJ
K
X
ADC and DAC Converters VHDL model
  • Xabier Iturbe
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6
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17K
rtl.engineer
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E
Modelsim+Xilinx Block Ram Collision warnings
  • eko
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0
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4K
eko
E
R
Using Constrained Integer instead of SLV
  • rickman
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14
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2K
rickman
R
D
a microcomputer design problem
  • denken
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3
Views
908
Mike Treseler
M
S
uninferred due to asynchronous read logic
  • Shannon
2
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25
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6K
Shannon
S
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Modelsim
  • Ken
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1
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1K
Mike Treseler
M
D
SPARTAN-3 - Design a function generator.
  • davidyau78
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0
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1K
davidyau78
D
S
stumped on syntax yet again!
  • Shannon
2
Replies
22
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4K
Rob Dekker
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H
Newbie. I´m not able to use shared variables !
  • HansWernerMarschke
Replies
4
Views
1K
Mike Treseler
M
H
Variable is interpreted as signal ???
  • HansWernerMarschke
Replies
6
Views
903
Mike Treseler
M
H
Can´t use assert together with range
  • HansWernerMarschke
Replies
1
Views
1K
KJ
K
H
Can I use 'POS to find a character in a array ?
  • HansWernerMarschke
Replies
2
Views
707
HansWernerMarschke
H
R
connect MUX to 7segment decoder???
  • Rezus+
Replies
1
Views
2K
Rezus+
R
K
Assigning Values to Enumerated Types
  • Kevin Neilson
Replies
9
Views
1K
Kevin Neilson
K
C
UNISIM Library problem
  • cvt
Replies
0
Views
4K
cvt
C
K
inout to inout
  • Ken
Replies
2
Views
1K
Aiken
A
V
Constants and functions question. Xilinx ISE error...
  • vxvoodoo
Replies
3
Views
3K
Mike Treseler
M
B
Best Method for Count without Rollover
  • Brad Smallridge
Replies
4
Views
968
Kevin Neilson
K
J
Timing issues !!! help help!
  • jaquesgrobler
Replies
0
Views
950
jaquesgrobler
J
G
Conversion of 'real' to 'std_logic_vector' ?
  • GeekWizard
Replies
0
Views
2K
GeekWizard
G
A
Good syntax for state machine
  • Adrian Jongenelen
Replies
0
Views
809
Adrian Jongenelen
A
F
quick question
  • FP
Replies
15
Views
975
rickman
R
K
Weird !!
  • Kausi
Replies
15
Views
1K
KJ
K
T
I2C bus multiplexing inside CPLD
  • Thomas
Replies
10
Views
10K
Nicolas Matringe
N
A
Gray counter
  • ast
2
Replies
22
Views
12K
omahens
O
J
Getting started with VHDL and Verilog
  • jraj.thakkar
Replies
2
Views
1K
Mike Treseler
M
S
Problem in creating dump using Modelsim
  • shakeelsultan
Replies
0
Views
793
shakeelsultan
S
G
Ripple chain logic in VHDL
  • Govinda
Replies
3
Views
1K
Govinda
G
S
implementing sorting algorithm
  • sigithidayat
Replies
5
Views
2K
Aiken
A
P
Register File access problem
  • Philipp Richter
Replies
15
Views
1K
Philipp Richter
P
H
Newbie question. Allocators unsupported ?
  • HansWernerMarschke
Replies
1
Views
1K
HansWernerMarschke
H
H
How to use a package ?
  • HansWernerMarschke
Replies
2
Views
2K
HansWernerMarschke
H
P
Connecting inout signal to out.
  • pallav
Replies
2
Views
2K
pallav
P
S
Multi-source in Unit <calc_module> on signal <disp_out>
  • shirodkarrakesh
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0
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1K
shirodkarrakesh
S
B
overflow of adder in VHDL
  • blckisle
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1
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2K
blckisle
B
N
simple vhdl alarm clock
  • naqiboy
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0
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2K
naqiboy
N
P
Simple conversion question
  • Peter Glar
Replies
8
Views
1K
Mike Treseler
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Finalizing my code
  • naqiboy
Replies
3
Views
888
jcayer
J
A
Cypress Warp 6.3 library management
  • agdepus
Replies
7
Views
5K
kva
K
M
ISCAS Benchmark information
  • marc
Replies
1
Views
1K
pallav
P
P
Question about port map?
  • pallav
Replies
3
Views
1K
pallav
P
N
Synthesizing error!!
  • ntxsoft
Replies
1
Views
788
jcayer
J
R
VHDL FSM problem, need help!
  • ro888
Replies
1
Views
1K
jcayer
J
R
Interface between floating-point and std_logic_vector signals.
  • Rain
Replies
4
Views
1K
Mike Treseler
M
H
Are there any free voice or audio codecs in VHDL ?
  • HansWernerMarschke
Replies
2
Views
1K
jtw
J
G
squaring numbers
  • gzidude
Replies
7
Views
2K
gzidude
G
B
std_logic_vector <= my_constant
  • Brad Smallridge
Replies
9
Views
934
Andy
A
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Newbie question, Enigma in VHDL
  • HansWernerMarschke
Replies
1
Views
1K
Mike Treseler
M
T
VHDL--how to invoke 2-dimmension array from another module
  • tarzandavid
Replies
1
Views
858
tarzandavid
T

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