VHDL

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comp.lang.vhdl
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ERROR:Xst:827 HELP Please!
  • oppenheimer
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2
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5K
oppenheimer
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Two processes with communication through a signal.
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5
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kennheinrich
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clock divider
  • FP
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1
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KJ
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Delta delay problem between multiple ports
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6
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Thomas Stanka
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64bit integer conversion
  • tanukichu
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0
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tanukichu
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VHDL - Second argument of writeline must have a constant value.
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0
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srajendar
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VHDL switch model
  • rickman
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10
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Rick
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signal is never used warning
  • mosh11
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1
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jeppe
J
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Shift register extraction fails
  • Philip Herzog
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16
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2K
Symon
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String to std_logic_vector
  • Shannon
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10
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10K
Shannon
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automatic firmware revision for VHDL
  • dejfson
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6
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Martin Thompson
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VHDL, arbitrary string length
  • eko
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3
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prasanthri
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HDL - simulation vs synthesis
  • digital pig
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1
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digital pig
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How do you initialize signals in VHDL?
  • Madhu
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7
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39K
dfriedman
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variable vs signal
  • benradu
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18
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Colin Paul Gloster
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Comparing more than one bits?
  • Rob
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3
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863
rickman
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Query: Contract position wages
  • jaspalbhullar
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7
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rickman
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Can I ignore peaks in simulation?
  • Florian
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6
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913
rickman
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generic maps based on an input signal
  • tahder
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1
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tahder
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Newline character
  • mikmak
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0
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mikmak
M
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Multiplier synthesis on vhdl
  • zenerz
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0
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zenerz
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Does this 'structure' exist in VHDL
  • crabbedh
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835
crabbedh
C
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Decimal to binary for comparison
  • Klaus Thiele
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5
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4K
jeppe
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test bench
  • predador
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858
predador
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CRC7 Input bits in Command and Response
  • beky4kr
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0
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beky4kr
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R
simpler stuff!!!
  • rickman
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10
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KJ
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Detect EOL
  • johnp
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2
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johnp
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VHDL document generation utilities
  • PatC
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10
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7K
Colin Paul Gloster
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Array in an entity declaration ?
  • Chabrie
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2
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911
Colin Paul Gloster
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Have I been boned?
  • rickman
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14
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rickman
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Using a vector as an index
  • M. Hamed
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1
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720
Dave
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Passing Generics into a Package File
  • Kevin Neilson
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3
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2K
KJ
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Xistinks
  • gzidude
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0
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722
gzidude
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What am I missing?
  • rickman
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13
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rickman
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Breaking News ... Accellera Verification Working Group Forming
  • HairyTheASICGuy
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8
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KarenB
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GPS Task Issues
  • corza
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1
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corza
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diference between signal and variable?
  • jonathan castro
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1
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797
jeppe
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wait for statement inside a process
  • carbon9
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1
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jeppe
J
X
Addition of 2 numbers
  • xcite
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0
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xcite
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ANNC: FPGA Design Software Webcast
  • bart
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10
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Robert Miles
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Convert enumeration to std_logic_vector
  • Stef
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7
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rickman
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Concurrent vs Sequential
  • VHDL_newb
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1
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jeppe
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Call for Papers with Extended Deadline of June 1, 2008: WORLDCOMP'08(CS & CE Conferences), July 200
  • A. M. G. Solo
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0
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A. M. G. Solo
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Multidimensional generic vhdl
  • Salman
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4
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8K
sLim
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how to get wallclock time between any two events (not simulation time) in vhdl
  • kevs
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3
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kevs
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simple stuff !!!
  • LC
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13
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rickman
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problem with assignment to output pin
  • jonathan castro
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5
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jonathan castro
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Modulator / Demodulator
  • john
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0
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john
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Problem with register file
  • Fi3rizi0
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0
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810
Fi3rizi0
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Coding rules?
  • Peter
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6
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1K
Mike Treseler
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