VHDL

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comp.lang.vhdl
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DSP newbie
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6
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1K
FPGA
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Think Silicon announces IP Partnership programme
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1K
Iakovos Stamoulis
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delta cycle?? (delta delay)
  • srikanth.padava
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0
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2K
srikanth.padava
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Re: Delta delay in vhdl
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2
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5K
srikanth.padava
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Process...
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5
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3K
srikanth.padava
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`timescale 1 ps / 1 ps(verilog command equivalent in VHDL.
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13
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16K
Kim Enkovaara
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B
Simulation Constant
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7
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1K
Andy
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ANNC: ADC to FPGA Interface Webcast
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2
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2K
a7yvm109gf5d1
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Easier Way to Do Structural Design
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0
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849
Hybr1dz
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xilinx simulator error
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0
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2K
Mihovil Frater
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c++ compilation error
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1
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730
scottcarl
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VHDL and Video
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1
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797
sky465nm
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Instantiation of verilog component
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0
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sadann
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how to reduce simulation time?
  • sheri
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1
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1K
Kim Enkovaara
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Skip indetation in Emacs vhdl-mode
  • xipn
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0
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798
xipn
X
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an error multiple sources
  • ViaTy
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0
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895
ViaTy
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please help me check my coding
  • raullim7
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1
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725
raullim7
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Sequential counters and Quatrus's RTL
  • john
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1
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1K
Dwayne Dilbeck
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Synthesis of functions in Quartus
  • FPGA
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2
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854
FPGA
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Seed Values
  • FPGA
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4
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1K
Paul Uiterlinden
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Kudos to Aldec
  • HT-Lab
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0
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929
HT-Lab
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error about 'can not have such operands in this context'
  • Zhi
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3
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4K
Zhi
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C
how to generate blockdiagram
  • chisti09
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5
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955
Mark McDougall
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strange compiler message
  • Rob Granger
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3
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7K
kennheinrich
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function declaration not found
  • Zhi
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3
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1K
gzidude
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Transport Triggered Architecture Socket in VHDL
  • lyonscf
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1
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1K
HT-Lab
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canny edge detection
  • saran
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1
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2K
KJ
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How to draw Logic Network from VHDL code
  • wave00
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3
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3K
Frank Buss
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vhdl code for ALN
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0
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713
ruwani
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The best way to synchronize
  • john
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9
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1K
Mike Treseler
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ATPG Vector Generation and Fault Coverage
  • moogyd
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3
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4K
Thomas Stanka
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software for beginners
  • cirutech
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4
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1K
cerocca
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Vhdl Program
  • sudeep
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4
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1K
sudeep
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Code coverage & Functional coverage tutorials
  • Raj
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4
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10K
asicvlsi
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clarification on generics
  • MattLFerraro
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12
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2K
KJ
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need help for adaptive logic N/W in VHDL
  • ruwani
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0
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858
ruwani
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Coding for CPLD vs FPGA
  • axr0284
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4
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1K
bryce.bolton
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Modelsim VCD files
  • Petter Gustad
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6
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9K
Dwayne Dilbeck
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Verilog Implementation of FIR Filter
  • Rahul Iyer
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1
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6K
gally
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How to use RLOC_ORIGIN
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0
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2K
graffitici
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Vhdl Test Bench
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0
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2K
michsib
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vcd help
  • vex_helix
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2
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892
vex_helix
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Synthesis-Place-Route benchmark for i386-32bit
  • fcdup8k
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1
Views
751
scottcarl
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J
HPCNCS-08 Draft paper submission deadline is just few days from now
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2
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867
scottcarl
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VHDL signal generation on FPGA...Help..
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4
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4K
Alan Fitch
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PC configuration for fastest compiles (synthesis, place and route,etc)
  • wallge
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1
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925
CM
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distorted sine wave
  • FPGA
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6
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2K
FPGA
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others and aggregates...
  • neilmac
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1
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1K
gzidude
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partioning made easy?
  • gzidude
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0
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842
gzidude
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canonical adder
  • sana
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1
Views
740
Mike Treseler
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