VHDL

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comp.lang.vhdl
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Detecting a pulse with minimum width
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3
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KJ
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multidimensional array
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Vijayant
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help
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2
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875
Mike Treseler
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Init RAM component
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jeppe
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Design entries for FSM
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jeppe
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Sonet Pointer justification Concept
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ekavirsrikanth
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spartan 3 design projects
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jeppe
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Computer hardware answers what you looking for...
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1
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846
Thomas Stanka
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simulating Xilinx cores
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1
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1K
hilal
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Latch problem in FSM
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1
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1K
jeppe
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Blast from the past
  • CTSportPilot
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10
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2K
CTSportPilot
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Unit testing vhdl using xUnit?
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3
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Martin Thompson
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Impact of Reset on Area
  • jshrini.vasu
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1
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741
naliali
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Sun open SPARC micro architecture document
  • Davy
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1
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1K
vysakhpillai
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Cannot Infer Wired-Or in Leonardo Spectrum
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2
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Rob Dekker
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translate_off/on tool interoperability
  • Rob Dekker
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5
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4K
Mike Treseler
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Buffer
  • shohreh
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3
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893
Dwayne Dilbeck
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conditional constant define
  • ramidamari
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0
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1K
ramidamari
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vhdl source code for DMA controller
  • VJ
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1
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6K
swapnav
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Out of Range - simulation vs. synthesis
  • ALuPin
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8
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2K
ALuPin
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about clock
  • Amit
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1
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724
Mike Treseler
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Reading .exe file in testbench
  • sagar_saga01
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0
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766
sagar_saga01
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Division with std_logic_vector
  • danell
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4
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5K
danell
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vga
  • ramsin
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6
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918
Amit
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Need help on LPM_ROM (Altera)
  • Amit
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4
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5K
ramsin
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Call For Papers with Extended Deadline of Mar. 10, 2008: The 2008International Conference on Modeli
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0
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1K
A. M. G. Solo
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2nd CFP: DATICS 2008 - Design, Analysis and Tools for IntegratedCircuits and Systems
  • ss.dtvcs
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0
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ss.dtvcs
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Interview questions ;)
  • Clemens Blank
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8
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6K
Thomas Stanka
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about timing.
  • Amit
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6
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865
JK
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verifying UNIFORM using matlab
  • FPGA
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7
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1K
ajjc
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About fsdb Dump using ncvhdl
  • ytfilter
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1
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4K
JK
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a Sample and hold circuit model
  • Manivannan
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1
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6K
cdbular
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Filling large ROMs
  • Xin Xiao
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5
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978
Mark McDougall
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FPGA/CPLD group on LinkedIn
  • wmwmurray
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2
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1K
wmwmurray
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indirection with strings containing signal names?
  • newdaddy
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5
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2K
jtw
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real to signed
  • FPGA
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11
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2K
FPGA
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WAIT UNTIL exit statement
  • Niv
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3
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5K
Niv
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ModelSim PE (student ed.) vs. Xilinx ISE Simulator
  • Mihovil Frater
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0
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5K
Mihovil Frater
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Random Number Generation in VHDL
  • FPGA
2
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20
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9K
Ray Andraka
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parse error: unexpected if in xilinx ise 8.1i
  • revu
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5
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4K
revu
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SDRAM controller design
  • neha.k.ee
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1
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4K
Rob
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ghdl unsigned
  • revu
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2
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1K
diogratia
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please help me..
  • anupamaasok
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4
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853
Thomas Stanka
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synthesising fixed_pkg
  • mvjijuaie
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2
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2K
David Bishop
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Counter verification
  • john
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3
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2K
Dave Pollum
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vhdl:data memory
  • agnese.rosi
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1
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942
Tricky
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DSP Ip core
  • Jean-sébastien LEROY
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1
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891
sly
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Simulation behaviour, explanation requested
  • Jyrki Takalo-Kastari
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8
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985
Jyrki Takalo-Kastari
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want VHDL code for this circuit-ergent!
  • ruwani
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1
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1K
gzidude
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Call For Papers with Extended Deadline: WORLDCOMP'08 (comp. sci.,comp. eng., and applied computing
  • A. M. G. Solo
Replies
0
Views
974
A. M. G. Solo
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