VHDL

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comp.lang.vhdl
J
Spartan kit
  • john
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1
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1K
RedskullDC
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simulation problems
  • FPGA
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5
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1K
Andy
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INOUT Vectors data is incorrect
  • Matt
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8
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1K
Duane Clark
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latches in vhdl
  • Xin Xiao
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10
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2K
Brian Drummond
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I
What does this do ?
  • iqbalmuh
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5
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1K
Symon
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round,fix and floor algortihms
  • FPGA23
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13
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22K
FPGA.unknown
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Verilog INOUT problem!
  • thomas_ns
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4
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7K
Andy
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B
Help in ISE Error: Xst:779
  • begin_ner
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0
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2K
begin_ner
B
A
Arrays in VHDL
  • Ann
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11
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2K
Andy
A
X
converting bitvector to integer
  • Xin Xiao
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9
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2K
Andy
A
M
HLL VHDL & VCD
  • Mayan Moudgill
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4
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1K
Colin Paul Gloster
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A
vhdl code
  • alf2reji
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2
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3K
kays_f
K
A
Synopsys Design Compiler VHDL Files
  • abttje
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0
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2K
abttje
A
X
is this synthesizable?
  • Xin Xiao
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4
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2K
Jonathan Bromley
J
X
wait for signal in process
  • Xin Xiao
Replies
1
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931
KJ
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X
Big signal assignment
  • Xin Xiao
Replies
6
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1K
Brian Drummond
B
B
help with file I/O and generic constants
  • bister
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3
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1K
bister
B
N
VHDL real numbers
  • Niv
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8
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3K
KJ
K
C
down counter VHDL
  • clarken
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0
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6K
clarken
C
H
design error
  • HaYZaM
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0
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854
HaYZaM
H
A
Verilog Question
  • Ann
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2
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741
Jonathan Bromley
J
S
Want solution for Shift/reduce conflict in VHDL grammar
  • saorjag1729
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0
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2K
saorjag1729
S
X
Variable or signal?
  • Xin Xiao
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2
Views
939
Xin Xiao
X
P
"and" every element of std_logic_vector
  • Peter Larsen
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4
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1K
Mayan Moudgill
M
A
help VHDL- verilog co simulation
  • absr
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2
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2K
flyfish866
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A
help!(rom code)
  • abc1010
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0
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1K
abc1010
A
K
.....Synthesizing signals
  • knight
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0
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828
knight
K
P
Fully definable ports of array of std_logic_vectors?
  • paragon.john
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5
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3K
Amal
A
D
ASIC verification job info request
  • Dwayne Dilbeck
Replies
4
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1K
Dwayne Dilbeck
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L
I need an Exponential function!!!
  • LeirbaG
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0
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2K
LeirbaG
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S
map error about input signals of state machine that will be trimmed
  • Steven Kauffmann
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2
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923
Steven Kauffmann
S
C
VHDL for add/subtract
  • clarken
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0
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3K
clarken
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M
Mixed VHDL and Verilog question
  • marcoa.castellon
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2
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3K
Dwayne Dilbeck
D
S
Multi-processor chips.
  • Symon
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2
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730
Mike Treseler
M
B
problem with vhdl
  • burigallego
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0
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772
burigallego
B
A
Call For Papers: WORLDCOMP'08: Computer Science & ComputerEngineering Conferences, USA, July 2008
  • A. M. G. Solo
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0
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1K
A. M. G. Solo
A
J
who is owner of this group?
  • JK
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2
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806
james
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K
VCS simulation for VHDL DUT and Verilog test bench
  • kartikey
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0
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3K
kartikey
K
D
wait statement
  • denko
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0
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997
denko
D
M
Not used inputs - what to do with it
  • MJ
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2
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759
Mike Treseler
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W
[help]SAS with FPGAs
  • westspeed
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1
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979
John_H
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E
need help... VHDL Variable problem...
  • elements_me
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0
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780
elements_me
E
A
Reading 2D array
  • ALuPin
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6
Views
950
dimhatzo
D
P
VHDL language is out of date! Why? I will explain.
  • psihodelia
2 3
Replies
41
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4K
MikeShepherd564
M
S
Glitches in Modelsim
  • sbreheny
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0
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2K
sbreheny
S
O
parsing a subtype_indication
  • Ole Nielsby
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2
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586
kennheinrich
K
K
Questa AVM
  • knight
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0
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820
knight
K
P
WSEAS
  • prof.bose
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0
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881
prof.bose
P
A
full adder example using fpga
  • Amit
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5
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2K
Amit
A
R
vhdl sobel for FPGA
  • rossalbi
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2
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2K
sprocket
S

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