VHDL

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comp.lang.vhdl
Z
shift_right/ shift_left
  • ZHIQUAN
2
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27
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21K
Mike Treseler
M
O
configuration problem
  • Olaf
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3
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1K
Olaf
O
Z
About textio
  • Zhi
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3
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2K
Zhi
Z
P
code 211 in modelsim / Xilinx ISE sim problem
  • palo
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0
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2K
palo
P
S
Multiple copies of an entity controlled by a parameter 'b'
  • scs9gp
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0
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729
scs9gp
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A
Calling functions declared in an entity
  • Andre
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4
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6K
Paul Uiterlinden
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J
Help with syntesis warnings
  • JnCodesigns
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2
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5K
scs9gp
S
B
how using files as input and outputs
  • beginner_vhdl
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2
Views
830
beginner_vhdl
B
O
gray counter and compare value
  • Olaf
Replies
4
Views
5K
Ahmed Samieh
A
V
fast synthesize
  • vbehravan
Replies
0
Views
752
vbehravan
V
E
driving "external" signals from a procedure
  • Eli Bendersky
Replies
15
Views
11K
Jonathan Bromley
J
P
Coding style for nested FSM?
  • Pleg
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8
Views
4K
Pleg
P
V
analog to digital converter
  • vsreejishav82
Replies
0
Views
894
vsreejishav82
V
T
VHDL Case Statement
  • The Hath
Replies
0
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9K
The Hath
T
M
Implementation of an up/down counter in a Xilinx Spartan 2E board
  • mrudhulbala
Replies
1
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2K
Mike Treseler
M
Z
How to use 'assert' and 'report'
  • ZHIQUAN
Replies
2
Views
1K
Andy
A
J
clock and stable data
  • john
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1
Views
1K
JK
J
K
dumpports:pullup and pull down (problem )
  • kasiviswa1983
Replies
0
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1K
kasiviswa1983
K
S
Post Synthesis, Post PAR, and real hardware behavior?
  • scott.yuan523
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5
Views
2K
Thomas Stanka
T
A
Question on bounce filter
  • Amit
Replies
0
Views
669
Amit
A
C
[how to make?] mux 1x1 128 bits + for generate
  • conradojr
Replies
5
Views
2K
Andy
A
S
how to download matlab program onto fpga
  • sandeep_sp7
Replies
0
Views
1K
sandeep_sp7
S
A
Modelsim simulation progress in batch/command line mode?
  • Andreas Ehliar
Replies
6
Views
7K
M. Hamed
M
V
generic gate netlist using Precision RTL
  • Vlad Ciubotariu
Replies
5
Views
2K
HT-Lab
H
M
Problems with resolved types and multiple drivers
  • Markus Jochim
Replies
5
Views
3K
Andy
A
D
BCD Counter
  • daveip
Replies
0
Views
2K
daveip
D
D
Decoder using VHDL
  • dkk1980
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0
Views
2K
dkk1980
D
P
nested if-elsif-then Vs case
  • palo
Replies
0
Views
2K
palo
P
S
Some System Verilog questions
  • sundar
Replies
0
Views
3K
sundar
S
S
Signal generator using FPGA and DAC
  • Sheetal
Replies
1
Views
2K
quantum_dot
Q
Z
How to write a testbench
  • ZHIQUAN
Replies
3
Views
2K
Mike Treseler
M
C
doubt in vhdl program and fpga ( key bebouncing)
  • chaitu
Replies
0
Views
1K
chaitu
C
K
generic compare in if statement help?
  • Kamachi923
Replies
1
Views
3K
Jim Lewis
J
A
question on async D's f/f
  • Amit
Replies
1
Views
853
Amit
A
G
VHDL syntax
  • Grumps
Replies
9
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2K
Jim Lewis
J
M
vhdl and ultraedit
  • mans
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0
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2K
mans
M
H
Problem with real data type
  • Hrishi
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0
Views
1K
Hrishi
H
C
PCB functional modeling
  • canadianJaouk
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1
Views
1K
FMF
F
A
TI Tap Controller std8980
  • Amal
Replies
3
Views
1K
Amal
A
Z
ModemSim cannot recognise 'SIGNED' type?
  • ZHIQUAN
Replies
1
Views
1K
ZHIQUAN
Z
R
School Project without success
  • Reload6156
Replies
0
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1K
Reload6156
R
G
Use BRam and DRam on FPGA's Xilinx
  • Gordon Freeman
Replies
5
Views
5K
Gordon Freeman
G
R
Simulink MDL to HDL Code
  • RashidY
Replies
0
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2K
RashidY
R
Z
Cannot transmit correct result consecutively
  • ZHIQUAN
Replies
13
Views
1K
ZHIQUAN
Z
O
Modelsim post place and route/Post Translate
  • orch
Replies
0
Views
2K
orch
O
A
left and low
  • Account1
Replies
6
Views
746
Brian Drummond
B
A
How to use Block RAMs ??
  • Asm4PIC
Replies
3
Views
1K
Asm4PIC
A
S
If Vs Case
  • SmiG
Replies
4
Views
2K
Mike Treseler
M
N
generate statement inside a process (conditional variable declaration)
  • Nicolas Matringe
Replies
5
Views
10K
Nicolas Matringe
N
N
Question about Ben Cohen's switch model
  • Nicolas Matringe
Replies
5
Views
1K
canadianJaouk
C

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