VHDL

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comp.lang.vhdl
A
Question on FIFO
  • Amit
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4
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1K
Paul Uiterlinden
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A
How can I flush file input buffers?
  • Anon Anon
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4
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3K
Mike Treseler
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floating number
  • Dkthechamp
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5
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1K
Paul Uiterlinden
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How many memory need for Convolution
  • ontos
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1
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1K
ontos
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C
visualise"type" in wave window
  • Clunixchit
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3
Views
962
Mike Treseler
M
A
Multiple sources ??? Example vhdl code - anyone can help ???
  • adamjoniec
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9
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2K
Mike Treseler
M
P
Define type based on function return in package?
  • Pentode
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2
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1K
Pentode
P
F
Differfence in the assignment of a variable to a signal with and without condition
  • filmil
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11
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2K
Mike Treseler
M
B
design flow questions
  • bhavanireddy
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4
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2K
Mike Treseler
M
3
How to Dart Game with VHDL
  • 300zx
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0
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1K
300zx
3
A
Are actions permitted on rising *and* falling edge of clock?
  • Anon Anon
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2
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2K
Andy
A
J
Simulation of VHDL in xilinx from a C program?
  • jesse lackey
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3
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2K
Günther Jehle
G
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Traffic light complete!
  • Hammer
Replies
8
Views
12K
JULIOSOL
J
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MODELSIM : library generation and mapping
  • Pasacco
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4
Views
13K
Duane Clark
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Modelsim 6.3 & VHDL2006
  • HT-Lab
Replies
2
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1K
Amal
A
A
Multiple sources ??? Example vhdl code - anyone can help ???
  • adam8024
Replies
0
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1K
adam8024
A
A
What you suggest?
  • Amit
Replies
4
Views
1K
mkr
M
N
Binary to BCD in VHDL
  • NA
Replies
3
Views
6K
NA
N
V
Custom Software Development
  • VB
Replies
0
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1K
VB
V
S
Node instance
  • Sushma
Replies
6
Views
2K
JK
J
M
component usage
  • mkr
Replies
7
Views
1K
Andy
A
V
Query about optimization
  • Vinay Deshpande
Replies
14
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2K
Andy
A
T
dual-edge sensitivity
  • travislagrone
Replies
2
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2K
scottcarl
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VHDL newbie: building sequential circuits with basic gates
  • GomoX
Replies
19
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3K
Andy
A
M
quwstion from newbie
  • mobi999
Replies
1
Views
1K
Paxwell
P
A
Call For Participation: WORLDCOMP'07: joint conferences in CS, CE, and applied computing, June 25-
  • A. M. G. Solo
Replies
0
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1K
A. M. G. Solo
A
A
UART Receiver Parity Check
  • Anson.Stuggart
Replies
2
Views
4K
Eric Smith
E
M
Initializing memory to random numbers
  • --MMS--
Replies
8
Views
4K
Mike Treseler
M
W
How to insert tab in Write() function in VHDL
  • Weng Tianxiang
Replies
3
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3K
Gabor
G
S
Reed Solomon Encoder
  • sai
Replies
1
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3K
Duane Clark
D
A
11bit or 12 bits ?
  • Amit
Replies
5
Views
1K
David M. Palmer
D
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How do I constraint multiple clock cycle in Altera?
  • news reader
Replies
1
Views
2K
Rajkumar Kadam
R
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Conditional "FOR..GENERATE" generic construct?
  • Pasacco
Replies
3
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1K
Pasacco
P
C
SystemC and TLM
  • confusedpp
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0
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1K
confusedpp
C
L
Double Clock Frequency
  • LearnVHDL
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1
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3K
scottcarl
S
R
Identifier issue
  • red_dragon
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1
Views
835
scottcarl
S
N
Same code ... Different results ...
  • Niall
Replies
1
Views
998
Andy
A
N
Conflicting results
  • Niall
Replies
2
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1K
Niall
N
D
intel 8279 VHDL code wanted
  • dijego82
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2
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2K
ssteinnj
S
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How do i make a race timerA in VHDL?
  • trickae
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0
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2K
trickae
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H
Single clock pulse transfer to different clock domains.
  • himassk
Replies
1
Views
2K
Paul Uiterlinden
P
O
CMOS camera-FPGA-USB
  • ontos
Replies
2
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5K
ontos
O
M
LF VHDL to FSM bubble diagram translator
  • MM
Replies
3
Views
3K
Mike Treseler
M
M
Need to delay a signal a great number of clk cycles
  • martin.wahlstedt
Replies
1
Views
3K
scottcarl
S
M
VHDL and Emacs (My experience)
  • mans
2
Replies
23
Views
8K
Mike Treseler
M
M
cache not a ROM, inferring, xilinx
  • --MMS--
Replies
2
Views
2K
--MMS--
M
M
two-dimensional array, assign to zero, vhdl
  • --MMS--
Replies
8
Views
9K
Andy
A
N
Timer ...
  • Niall
Replies
18
Views
2K
Martin Thompson
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C
Anyone using the TimingAnalyzer
  • chewie54
Replies
3
Views
1K
chewie54
C
A
Urgent Question.
  • Amit
Replies
1
Views
1K
Mike Treseler
M

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