VHDL

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comp.lang.vhdl
N
Does VHDL have a statement similar to "event" in Verilog?
  • news reader
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2
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2K
Evan Lavelle
E
C
USB NRZI encoding and bit stuffing question
  • cxu_dl
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9
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8K
Andy Peters
A
J
subtype question
  • John Smith
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1
Views
861
Jim Lewis
J
D
memory implementation
  • dashdingo
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0
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677
dashdingo
D
F
More width issues in Synplify Pro 8.8
  • filmil
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4
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1K
Filip Miletic
F
C
How Do Perform STD_LOGIC_VECTOR Addition Using IEEE.NUMERIC_STD?
  • Chris
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10
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2K
Chris
C
T
counter with reset which is synchronous with one of two clocks
  • Thunder
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4
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1K
Jonathan Bromley
J
F
Width issues in Synplify Pro 8.8
  • filmil
Replies
0
Views
966
filmil
F
T
Timing details during synthesis in Xilinx ISE
  • Thunder
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2
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1K
KJ
K
R
a crazy problem
  • Rock Lee
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0
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984
Rock Lee
R
T
'for' loops in VHDL
  • Thunder
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3
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42K
Andy
A
C
Vhdl C++
  • clare77
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0
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970
clare77
C
T
access internal signal in VHDL from verilog
  • tkvhdl
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4
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5K
tkvhdl
T
A
Problem with ASSERT ... REPORT and NUL
  • Analog_Guy
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10
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1K
Mike Treseler
M
O
"IF" condition & STD_LOGIC_VECTOR
  • ontos
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0
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1K
ontos
O
S
VHDL and Verilog - 15 x Contract Engineers Required Urgently - Long Term Contract
  • Specialist Verilog Engineers Roles
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0
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1K
Specialist Verilog Engineers Roles
S
M
Delay in FSM using one process
  • maurizio.gencarelli
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2
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2K
Martin Thompson
M
M
My FSM is jumping to an unreachable state
  • maurizio.gencarelli
Replies
5
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1K
Niv
N
V
VHDL to Verilog conversion
  • vasim98
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2
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2K
scottcarl
S
C
Counter in FSM doesn't work
  • cpudesigner
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5
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1K
Jonathan Bromley
J
L
Tdm Bidirectional Serial Line
  • Lukas
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0
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1K
Lukas
L
A
Cadence TestBuilder
  • Amal
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4
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1K
Evan Lavelle
E
O
Synthesis of variable index array
  • oshouman
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3
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4K
oshouman
O
O
Procedure call
  • oshouman
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0
Views
856
oshouman
O
A
VHDL Eclipse Plugin
  • andywagner3
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2
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19K
andy.wagner2
A
M
Questions about single process coding style
  • Mike Treseler
2
Replies
24
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3K
Mike Treseler
M
L
GHDL and Xilinx
  • lelesa
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7
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5K
Kees Bakker
K
J
two .vhd sources in a project... ISE 9.1 ?
  • jesse lackey
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4
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1K
scottcarl
S
B
Question on importing text from files
  • boingboing
Replies
1
Views
953
scottcarl
S
T
Synchronize incoming singal to clock
  • TheThunder
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13
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2K
Laurent Pinchart
L
B
ANNC: LatticeXP2 FPGA Introduction Webcast
  • bart
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0
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1K
bart
B
A
Accellera VHDL 2006 LRM
  • Amal
Replies
7
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1K
David Bishop
D
P
32-Bit Fixed Point Divider Needed
  • phuxua...
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3
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2K
David Bishop
D
A
RC4 - someone help pleas!!
  • Ahmed Samieh
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12
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2K
Ahmed Samieh
A
T
CORDIC algorithm in vhdl
  • tonololotono
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0
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2K
tonololotono
T
A
What does "others : begin NO" mean?
  • Altera User
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3
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822
Mark McDougall
M
O
Time of Synthesis
  • oshouman
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0
Views
678
oshouman
O
O
Case Statement understood as FSM
  • oshouman
Replies
0
Views
921
oshouman
O
A
Generic RAM Implementation
  • ashishb4u
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0
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1K
ashishb4u
A
J
low attribute
  • John Smith
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1
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613
Jonathan Bromley
J
A
funtions
  • Al
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10
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1K
Jonathan Bromley
J
D
i can't simulate with modelsim XE III 6.2C
  • DaVidL
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2
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1K
DaVidL
D
R
EPP Data Write Cycle
  • Rodrigo Ribeiro
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0
Views
855
Rodrigo Ribeiro
R
C
modelsim 6.3 license
  • Clunixchit
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7
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12K
Thomas Stanka
T
B
Lattice's Online Store Now Sells Silicon - No Minimum Order Quantity
  • bart
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14
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2K
Didi
D
J
str to stdvec of converted values
  • J_R_L
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0
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2K
J_R_L
J
M
shift/rotate operator for std_logic_vector
  • Marteno Rodia
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1
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5K
Mike Treseler
M
S
Method cannot have a parameter of file type
  • sgregnt
Replies
4
Views
1K
James Unterburger
J
T
DCM clock signal output
  • TheThunder
Replies
1
Views
1K
Andy Peters
A
M
LFSR
  • mn19
Replies
1
Views
1K
Mike Treseler
M

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