VHDL

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comp.lang.vhdl
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In VHDL testbench, how do I probe internal signal of an entity?
  • G Iveco
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6
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6K
HT-Lab
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Code for 24 mhz to 434Khz..
  • shah_satish2002
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0
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791
shah_satish2002
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VHDL style question
  • vu_5421
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10
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2K
Jonathan Bromley
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How in VHDL do I write formatted spreadsheet file of my signals?
  • G Iveco
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2
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1K
Ralf Hildebrandt
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Mixed Simulation of Design (VHDL and Verilog)
  • Mirza
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11
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7K
Paul Uiterlinden
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FSM going crazy
  • Timo Gerber
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2
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797
Ajeetha (www.noveldv.com)
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How in VHDL do I concatenate a bit many times?
  • G Iveco
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3
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47K
Jonathan Bromley
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Dumping real signals in VCD
  • Sajan
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8
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9K
vlsi.engg27
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Error in 8 Shift register right code
  • shah_satish2002
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0
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939
shah_satish2002
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Help...Do anyone know how to exit modelsim(vsim) by using perlscript??
  • tuspa
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0
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1K
tuspa
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K
Scope of selected names in context/use clause
  • kennheinrich
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3
Views
884
Mike Treseler
M
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Dual Port RAM Simulation
  • Scott
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5
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2K
ALuPin
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Access order and LE reduction in FORTH chip
  • jacko
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0
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722
jacko
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Req: (Free) Embedded Platforms for Education
  • gouaich
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1
Views
646
NigelE
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Dual Port RAM Simulation
  • Scott
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0
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1K
Scott
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How add libary in ISE??
  • Tomasz Turek
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1
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805
Tomasz Turek
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How to make equal value
  • shah_satish2002
Replies
0
Views
747
shah_satish2002
S
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Is this statement legal?
  • Immocation
Replies
1
Views
763
Tomasz Turek
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Sample code
  • shah_satish2002
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0
Views
757
shah_satish2002
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J
Problem with simple VHDL piece of code
  • Jaco Naude
Replies
9
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1K
Andy
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Code for programming Flash memory
  • lyndonamsdon
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8
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4K
lyndonamsdon
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Synthesis of pure and impure functions
  • konstantink
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1
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2K
Mike Treseler
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sequence detector dode required...
  • kil
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6
Views
1K
Marcus Harnisch
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Help with Libero IDE and Verilog
  • weg22
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1
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2K
Mike Treseler
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good advanced digital question
  • mayurvlsi
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0
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739
mayurvlsi
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M
Setup n hold time
  • mayurvlsi
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0
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1K
mayurvlsi
M
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Using logical operators on parameterized-length vectors
  • tristan.denhond
Replies
7
Views
1K
Mike Treseler
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VHDL File Declarations
  • cory_in_texas
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0
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718
cory_in_texas
C
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xilinx ISE8.2 error: XST779
  • JayTee
Replies
1
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1K
sridar
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Array of array as in C ? how in vhdl!
  • tech2007
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0
Views
950
tech2007
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Interfacing DDR RAMs to Xilinx Virtex 2 Pro on Digilent boards
  • koustav79
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1
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2K
kunal
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P
write in same file with several procedure
  • picnanard
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0
Views
654
picnanard
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shut down problem during place and route.
  • sheri
Replies
6
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1K
Martin Thompson
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What is the meaning of a signal in VHDL
  • parag_paul
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13
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4K
Mike Treseler
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Newbe VHDL Help
  • c130herc
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0
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674
c130herc
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Simulators exit suddenly
  • oshouman
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1
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1K
scottcarl
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test bench
  • roussey
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1
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985
scottcarl
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Two processes sending data on same output
  • salmanghafoor1
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1
Views
674
scottcarl
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How to call verilog file as a PACKAGE in VHDL.
  • dipesh.trivedi
Replies
2
Views
2K
Niv
N
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Instancing
  • Immocation
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0
Views
763
Immocation
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E
regarding conversion of form std_logic_vector to std_logic
  • ekavirsrikanth
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4
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1K
ekavirsrikanth
E
Q
vhdl code for bidirectional transciever
  • qtr
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0
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1K
qtr
Q
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Easy type conversion question for you guys
  • Shannon
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3
Views
814
Mike Treseler
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advance simulation time without running
  • anupam.jain21
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6
Views
1K
anupam.jain21
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Integer in port declaration?
  • Lenny
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9
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2K
KJ
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On HDL Synthesis
  • devices
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12
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1K
devices
D
C
Can I Pass a 2D Array as a Parameter to a Procedure?
  • Chris
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4
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3K
Mike Treseler
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default value for subprogram parameter
  • John Smith
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10
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1K
Jonathan Bromley
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VHPI Books and/or Tutorials
  • PlayDough
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0
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1K
PlayDough
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clock delay when testing different inputs in FSM ?
  • maurizio.gencarelli
Replies
6
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1K
maurizio.gencarelli
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