VHDL

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comp.lang.vhdl
D
Initialize of Bram.
  • dinesh_14feb
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938
dinesh_14feb
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Regarding Simulation of Block RAM
  • dinesh_14feb
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797
dinesh_14feb
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How to stop Infinite loop
  • shah_satish2002
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0
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1K
shah_satish2002
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Memory Inference
  • sridar
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0
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803
sridar
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How do I declare CFILE variables with global visibility?
  • G Iveco
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6
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950
Mike Treseler
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mulitdimensional array at port configurations...
  • Dkthechamp
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10
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1K
Andy
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J
DAC would this be ok?
  • jacko
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6
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1K
industrial_one
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R
Which PSL is included in the VHDL-200X LRM sent to IEEE for approval?
  • Reuven
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4
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1K
Colin Paul Gloster
C
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Is it possible to write functions in VHDL with implicit parameters?
  • G Iveco
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4
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3K
Ralf Hildebrandt
R
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How do I correct this error?
  • G Iveco
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6
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2K
G Iveco
G
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2 bit selection ina register VHDL
  • Govinda
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3
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1K
Govinda
G
V
World's 1st FPGA Centric Portal goes LIVE!!
  • vkr101
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0
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1K
vkr101
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Best CPU platform(s) for FPGA synthesis
  • jjohnson
2
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33
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5K
Guest
G
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automatic documentation for vhdl
  • kjangkun
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3
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2K
Bill Mills
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G
generate stimulus in a 'do' file
  • Guy_Sweden
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3
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2K
Chris Shenton
C
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Signal in a Case Statement
  • Shannon
2
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22
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2K
Paul Uiterlinden
P
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Use of rem in VHDL
  • salmanghafoor1
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0
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3K
salmanghafoor1
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D
File reading issue
  • Dkthechamp
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5
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780
Dkthechamp
D
A
library path problem
  • AG
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4
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833
AG
A
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Type conversion and std_logic_vector incrment
  • Govinda
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0
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942
Govinda
G
C
Software Reset with Virtex4's PowerPC and XilKernel
  • Closter
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1
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1K
JK
J
M
short integer equivalent
  • mk.supriya
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10
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1K
Andy
A
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Procedure for creating a signal from file
  • solosys
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0
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640
solosys
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Hardware connection to FPGA
  • shah_satish2002
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0
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812
shah_satish2002
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S
Assigning value
  • shah_satish2002
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0
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788
shah_satish2002
S
Z
generating
  • zlotawy
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1
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1K
Jonathan Bromley
J
M
please help me with this pc of code
  • mk.supriya
Replies
2
Views
703
mk.supriya
M
K
2 Multiplied clock sync.
  • klior
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0
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831
klior
K
V
code for FIFO implementation using block RAM
  • vibeni
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0
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2K
vibeni
V
S
Code not working for Quartus 2
  • shah_satish2002
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0
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4K
shah_satish2002
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E
Need Recommendation for VGA hardware design books
  • everkids
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1
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1K
everkids
E
B
Swapping Modules
  • Brad Smallridge
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4
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904
Andy
A
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OT: Do we deserve an acknowledgement?
  • Jonathan Bromley
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10
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1K
Shannon
S
J
Concurrent assignment Modelsim problem. Please, need help ASAP.
  • jason12
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0
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1K
jason12
J
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Modeling pullup on the input
  • YK
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5
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4K
ast
A
M
array-cam-compile problem
  • menmas
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2
Views
675
scottcarl
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B
Simulating clock drift
  • bwilson79
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1
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1K
bwilson79
B
M
for loop problem
  • mk.supriya
Replies
8
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792
mk.supriya
M
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Vector Comparison
  • solosys
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0
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594
solosys
S
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round robin arbiter
  • rt.surya
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1
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10K
Günther Jehle
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S
Send and receive bit in one clock
  • shah_satish2002
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0
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757
shah_satish2002
S
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2 D array initialization
  • mk.supriya
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8
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1K
mk.supriya
M
J
VHDL style and possible problems for first time user
  • jacko
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14
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2K
Andy
A
N
"Target of signal assignment is not a signal"
  • Nicolas Moreau
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9
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10K
Andy
A
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Use of libraries
  • PlayDough
2
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32
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4K
Martin Thompson
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ghdl 0.26 - NULL access dereferenced
  • Pinhas
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1
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1K
Paul Uiterlinden
P
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Specifying clock requirements for derived clocks...
  • Markus Jochim
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1
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2K
devices
D
P
General question on access SRAM
  • picnanard
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0
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832
picnanard
P
A
Automatic Schematic Generation (System Graph) and Viewer
  • Alfonso Acosta
Replies
4
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1K
Shannon
S
S
How to use Output pin as a input
  • shah_satish2002
Replies
0
Views
875
shah_satish2002
S

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