VHDL

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comp.lang.vhdl
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About the values in VHDL std_logic_vector
  • parag_paul
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3
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1K
Jonathan Bromley
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Error in HDL designer
  • roche.alexis
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5
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6K
HT-Lab
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Glitch Problem
  • Steve.Minshull
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4
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1K
Laurent Pinchart
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Beyond Newbie Question
  • mottoblatto
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8
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710
Paul Uiterlinden
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problem with VHDL 93 style file_open
  • skiggeboi
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0
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3K
skiggeboi
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Utilizing Device Specific RAM
  • Shannon
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9
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1K
Mike Treseler
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how to convert integer to signal value
  • Guffi
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2
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919
Guffi
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overloading 'operators in VHDL
  • Dolphin
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1
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1K
Andy
A
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synthesizable delay using vhdl
  • ravi33811
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0
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2K
ravi33811
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Synchroizing a counter with another signal
  • tonyfai
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0
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2K
tonyfai
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library conflict
  • Russell
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0
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715
Russell
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A
Finding signal types within Modelsim using TCL
  • aclegg1986
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1
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2K
Jonathan Bromley
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Problem in CRC check
  • sridar
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0
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835
sridar
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What is called carry chain structure in FPGA is called in IC?
  • Weng Tianxiang
Replies
6
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1K
glen herrmannsfeldt
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New keyword 'orif' and its implications
  • Weng Tianxiang
4 5 6
Replies
113
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5K
Mike Treseler
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Using packages in a hierarchical design
  • Shannon
Replies
9
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2K
Brian Drummond
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ASCII File
  • priya
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3
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1K
devices
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Reading non-text files
  • Tricky
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6
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2K
Huibert J. Lincklaen Arriens
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1/2 Convolutional Encoder
  • mits130
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1
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1K
Niv
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What is the name of Altera latest and most advanced chip serial that is competable in technology wit
  • Weng Tianxiang
Replies
2
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1K
Weng Tianxiang
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library interaction within Modelsim
  • aclegg1986
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4
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2K
Mike Treseler
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Style Question for Components
  • Shannon
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11
Views
943
Andy
A
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pst translate simulation
  • priya
Replies
1
Views
892
priya
P
Z
Xilinx ISE Project Navigator 8.1i
  • zlotawy
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1
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3K
=?ISO-8859-15?Q?Ludwig_H=FCgelsch=E4fer?=
?
I
ISQED08 Call for Papers
  • ISQED
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0
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906
ISQED
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Shift right : does not compile in Modelsim VCOM
  • Pasacco
Replies
4
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13K
Pasacco
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How do I fix this conversion problem?
  • G Iveco
Replies
1
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3K
Alain
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New keyword 'OIF' and its implications
  • Weng Tianxiang
Replies
0
Views
761
Weng Tianxiang
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free vhdl and verilog books
  • muffadal
Replies
1
Views
985
Brian Drummond
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Error while Simulation
  • sridar
Replies
0
Views
755
sridar
S
S
Testing tool required
  • sridar
Replies
0
Views
610
sridar
S
R
vhdl e book required
  • ravi33811
Replies
0
Views
779
ravi33811
R
C
asynchronous reset, simulator doesn't support
  • Clunixchit
Replies
9
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1K
Clunixchit
C
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function exp(z: complex)
  • Zhi
Replies
8
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2K
Zhi
Z
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Null statement in VHDL
  • Weng Tianxiang
2
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26
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3K
Andy
A
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CfP: EvoHOT 2008
  • squillero
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0
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1K
squillero
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S
VHDL'87: avoiding FATAL ERROR when "Failed to open VHDL file" occurs
  • sigwalt
Replies
2
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3K
kenm
K
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simple and annoying
  • David Binnie
Replies
6
Views
741
ast
A
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Exact simulation time in ModelSim
  • Jaco Naude
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3
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3K
HT-Lab
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XUP Virtex II Pro Exalauation board..
  • suddy72
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0
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953
suddy72
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delay code.
  • suddy72
Replies
0
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961
suddy72
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This code works in simulation but not in reality, please help
  • FranzH
Replies
19
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2K
Pieter Hulshoff
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RANGE attribute use
  • Shannon
Replies
4
Views
707
Shannon
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Orif Others
  • Brad Smallridge
Replies
2
Views
942
Brian Drummond
B
C
n gate delay
  • colin
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12
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1K
colin
C
A
VHDL-200x update?
  • Amal
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12
Views
1K
KJ
K
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Simulation cycles???
  • Karim_10
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0
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1K
Karim_10
K
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downto vs. to
  • Fabian
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4
Views
13K
Brad Smallridge
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Generic Arrays
  • Joachim Parsch
Replies
3
Views
1K
KJ
K
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VHDL-problem with symmetrical frequency divider by 3
  • Winfried Salomon
Replies
12
Views
15K
tsachg
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