VHDL

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comp.lang.vhdl
V
vector assignment in VHDL
  • Vadim Rusu
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3
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33K
ZOLVEZ
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Generic multiplexer
  • VladimirMatvejev
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1
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3K
Andy
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out ports on the right side
  • John Smith
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11
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1K
Jim Lewis
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PLL Lock Detect
  • moogyd
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4
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5K
moogyd
M
J
resol
  • John Smith
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3
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926
KJ
K
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integer to std_logic_vector if width not known apriori?
  • JimG
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0
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1K
JimG
J
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Problem with ModeltSim XE
  • zlotawy
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4
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709
zlotawy
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A
johnson ring counter and how to simulate it
  • Amit
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5
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6K
Amit
A
S
/ and rem, is it synthesizable if the first operand is a power of 2?
  • sonny
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2
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1K
Andy
A
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modelsim
  • vishii4u
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0
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873
vishii4u
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J
VHDL test bench stimuli; reading from a file with control
  • janaka
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1
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1K
veevee1
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S
Output data to textfile ??
  • suddy72
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1
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1K
veevee1
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VHDL 2 VERILOG CONVERTER FOR AHB
  • terabits
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4
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5K
mayankmehta_83
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Guess: what is the largest number of state machines in a current chip design: 1k, 10k, or...
  • Weng Tianxiang
2 3 4
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63
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4K
Weng Tianxiang
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P
"does not match a standard flip-flop"
  • Paul Burke
Replies
8
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8K
Andy
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SysC and VHDL cosimulation in modelsim
  • pupoo
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0
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1K
pupoo
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O
Testbench's configuration problem
  • Olaf
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1
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3K
Mike Treseler
M
H
AMS
  • Hosszu Gabor
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4
Views
1K
moogyd
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A
How to get two different clock
  • Amit
Replies
7
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979
Amit
A
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Answer: maximum number of state machines in a current chip: > 500k
  • Weng Tianxiang
Replies
6
Views
1K
ghelbig
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Look up table implemantation using Luts
  • ashu
Replies
1
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882
Shannon
S
S
Viewing memory data in core generator.
  • suddy72
Replies
0
Views
609
suddy72
S
U
ANNOUNCE: Embedded hw/sw developer freebies by Nikolaos Kavvadias
  • Uncle Noah
Replies
0
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823
Uncle Noah
U
J
drivers q.
  • John Smith
Replies
2
Views
704
John Smith
J
S
Initializing 2 block rams
  • Shannon
Replies
6
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3K
Shannon
S
A
Problem with waveform and ...
  • Amit
Replies
2
Views
1K
Amit
A
P
I am seeing 3 message against some posts but when I open I get on ly 1 of them
  • parag_paul
Replies
1
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761
Mike Treseler
M
P
What is the purpose of the access system in VHDL:
  • parag_paul
Replies
2
Views
779
Paul Uiterlinden
P
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How can I simply invert the floating point number?
  • Siwat Saibua
Replies
1
Views
1K
Siwat Saibua
S
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[ANNOUNCE] YARDstick - custom processor development toolset
  • Uncle Noah
Replies
12
Views
2K
Uncle Noah
U
S
related and unrelated logic
  • Szymon Janc
Replies
2
Views
815
David Spencer
D
I
clock multiplier with factor 1.5 or 3
  • Intec
Replies
2
Views
2K
Intec
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I
Can a signal be resolved as 'most recent event wins'?
  • Iwo Mergler
Replies
10
Views
2K
Paul Uiterlinden
P
O
How can I use IEEE.std_logic_textio.all?
  • obaskirt
Replies
0
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2K
obaskirt
O
J
sim cycle
  • John Smith
Replies
5
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1K
Jim Lewis
J
J
Calling custom defined hardware in a process
  • joseph
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4
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733
avimit
A
P
Asynchronous sequential always block with 2 clock signals
  • Prashanth Rao
Replies
0
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884
Prashanth Rao
P
B
ANNC: PCI Express and Ethernet Gaskets Webcasts
  • bart
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0
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895
bart
B
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Using BRAM in state machines
  • zoki111
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0
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1K
zoki111
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C
Handshake
  • Chris Maryan
Replies
4
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4K
Tricky
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Shared variable cannot be declared before the protected type body
  • Paul Uiterlinden
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2
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2K
Paul Uiterlinden
P
C
sounds
  • carlmorada
Replies
3
Views
955
Shannon
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N
SR Flip Flop
  • Nirav
Replies
16
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2K
Mike Treseler
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J
Floating point Mathematics
  • Joseph
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2
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792
Tricky
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C
component configuration, default binding, ModelSim
  • chi
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3
Views
11K
sreeram
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image processing in vhdl/verilog
  • mk.supriya
Replies
4
Views
3K
vmalkumar
V
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Lookup Table As Memory
  • sridar
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1
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869
vmalkumar
V
Q
logical problem !
  • quantum_dot
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0
Views
717
quantum_dot
Q
G
About "metavalue detected, returning FALSE" warning..
  • G Iveco
Replies
2
Views
10K
David Bishop
D
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ceil and floor
  • zlotawy
Replies
4
Views
13K
KJ
K

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