VHDL

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comp.lang.vhdl
B
Cast natural to std_logic_vector (and the other way)
  • badwolf500
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0
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2K
badwolf500
B
H
SDF file parsing
  • helix
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2
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2K
Colin Paul Gloster
C
S
Safe finite state machine design
  • SomeDude
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3
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4K
arant
A
V
latch inferrence in clocked process
  • vu
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3
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2K
arant
A
M
synthesizable AM2901 and family bit slice models?
  • Mike Kopp
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4
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3K
Eric Smith
E
M
Xilinx memories
  • Marc Jeambrun
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3
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1K
Eric Smith
E
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Fixed_pkg: PRoblem using ABS operator
  • Ved
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8
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3K
David Bishop
D
A
Signal Initialization Confusion
  • Analog_Guy
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1
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3K
Ajeetha
A
N
Number of Logic Elements Estimate
  • nfirtaps
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4
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2K
nfirtaps
N
H
New Book: A Pragmatic Approach to VMM Adoption // for TB designs
  • hdlcohen
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1
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2K
nishit
N
E
Questions relating to Xilinx XST toolbox
  • elements
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0
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1K
elements
E
C
records in port declarations
  • Christian Schleiffer
Replies
6
Views
4K
Amal
A
E
Use of real type signals for DSP core
  • Erik Verhagen
Replies
3
Views
3K
Ben Jones
B
C
Is VHDL+FPGA knowledge useful for Embedded engineer?
  • Chandresh
Replies
11
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7K
D Stanford
D
A
Virtual Signals in Modelsim
  • a1_nocrap_exh
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3
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4K
Mike Treseler
M
V
convert variables into signal
  • vasim98
Replies
0
Views
869
vasim98
V
A
Code Style - Default Value of Signal in Process
  • Analog_Guy
Replies
19
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1K
Andy
A
K
-RELAX in ncsim.
  • kk
Replies
3
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2K
Ajeetha
A
L
Synchronizing logic to a clock egde
  • lloyd.rochester
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2
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4K
homoalteraiensis
H
M
RAM simulation models
  • manusha
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3
Views
3K
homoalteraiensis
H
W
Where are Huffman encoding applications?
  • Weng Tianxiang
Replies
16
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10K
Weng Tianxiang
W
G
asynchronous counter an Xilinx FPGA for a newbie
  • Georges Konstantinidis
Replies
12
Views
8K
ckyz
C
K
equivalent of defparam in vhdl.
  • kk
Replies
4
Views
7K
Rob Dekker
R
N
VHDL designer's toolkit
  • Nicolas Matringe
Replies
8
Views
1K
Nicolas Matringe
N
A
Problems compiling with ISE Webpack 8.2.01i
  • aijazbaig1
Replies
2
Views
2K
Jim_B
J
?
library clause
  • =?ISO-8859-1?Q?Sch=FCle_Daniel?=
Replies
5
Views
850
Andy
A
?
shared variable
  • =?ISO-8859-1?Q?Sch=FCle_Daniel?=
Replies
10
Views
2K
Andy
A
S
How To Control The Z Modeling In Lec(formal Verification Tool)??
  • subhash
Replies
0
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1K
subhash
S
D
future in VLSI
  • Deepti
Replies
1
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3K
Abs
A
P
File read
  • pan
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0
Views
808
pan
P
J
FPGA LABVIEW programming
  • john
Replies
3
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6K
Mike Treseler
M
F
standard function for calculating the number of bits of a natural number?
  • Frank Buss
Replies
3
Views
5K
Mike Treseler
M
A
Problems compiling with ISE Webpack 8.2.01i
  • aijazbaig1
Replies
0
Views
1K
aijazbaig1
A
P
Metric tool for Java
  • pradeep.sel
Replies
0
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1K
pradeep.sel
P
L
HELP. How to generate a single delayed pulse strobe in VHDL
  • LRCR
Replies
3
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15K
bm
B
C
HELP:What is the difference between asynchronous and synchronous counter?
  • ckyz
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0
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5K
ckyz
C
A
74xx series TTL library avaliable?
  • ajcrm125
Replies
6
Views
9K
Andy
A
B
Importing a Xilinx system generator design into a bigger system
  • boysr2003
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0
Views
2K
boysr2003
B
R
Parser to convert a state machine written in VHDL to .dot format readable by graphviz
  • reuven
Replies
1
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2K
Mike Treseler
M
B
Switching to numeric_std
  • Brad Smallridge
Replies
4
Views
7K
Andy
A
J
Clock signal remains HIGH forever in Spartan-3 Starter Kit from Digilent
  • Javi
Replies
2
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2K
Javi
J
U
Character Map with Xilinx FPGA
  • usenet
Replies
3
Views
6K
Martin Thompson
M
S
Modelsim SE Simulation Question
  • Simon Heinzle
Replies
5
Views
2K
Bill Mills
B
W
How to print a state flow graph for a state machine using Xilinx ISE or ModelSim
  • Weng Tianxiang
Replies
3
Views
3K
Weng Tianxiang
W
J
RNG for FPGA
  • Jerome
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0
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1K
Jerome
J
H
Information/specification -- LXT2 format
  • Harish Sundararaj
Replies
1
Views
4K
bybell
B
E
Rom implementation
  • etoktas
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0
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3K
etoktas
E
M
why "setup-time and hold-time"?
  • maazbecin
Replies
0
Views
4K
maazbecin
M
V
Constant and signal problem in VHDL
  • Ved
Replies
3
Views
5K
Ved
V
M
[noob] signed binary
  • Massi
Replies
18
Views
2K
Jonathan Bromley
J

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