VHDL

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comp.lang.vhdl
M
have some problems with Lookup Table..
  • MiP
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3
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3K
Niv
N
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Xilinx GPIO help...
  • Dave
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0
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2K
Dave
D
V
plz help me
  • vidaencileo
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0
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883
vidaencileo
V
S
Accessing Text files
  • strykaar
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0
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801
strykaar
S
H
designing switch
  • hema
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1
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812
Mike Treseler
M
V
serial clock generation
  • vu
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2
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962
Benjamin Todd
B
J
No clock signals found in design
  • Jerry Johns
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0
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1K
Jerry Johns
J
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passing status register bits
  • Marco
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6
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1K
KJ
K
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Is it possible to watch variables and signals during debug?
  • Dufour
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12
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7K
Mike Treseler
M
A
Timing Simulation - (ModelSim)
  • Abs
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7
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15K
Hubble
H
S
Using Altera LPM megafunctions in Quartus II and VHDL in general
  • Shannon
2
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20
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14K
fp
F
J
MISC CPU Design
  • jacko
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1
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1K
jacko
J
D
Global signal conservation
  • David Ashley
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1
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875
jtw
J
M
sampling rate
  • Marco
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3
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1K
Thomas Fischer
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J
No clock signals found in design...
  • Jerrie85
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2
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1K
Jerrie85
J
M
rotary swith
  • martstev
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0
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945
martstev
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D
Quick synthesis question
  • David Ashley
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2
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3K
David Ashley
D
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std.textio and ieee.std_logic_textio procedure overloading
  • Magne Munkejord
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1
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6K
Magne Munkejord
M
M
Back on vhdl.. and on processes..
  • Massi
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10
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1K
jens
J
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VHDL mailboxes
  • Verification Consultant
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2
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2K
Reuven
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Floating point multiplier
  • mailmekaran
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0
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1K
mailmekaran
M
A
Davies-meyer in VHDL
  • Adam
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2
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1K
Adam
A
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FSM State transition coverage
  • hari_krishna
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0
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1K
hari_krishna
H
C
Xilinx synthesis problem
  • Christian Gelinek
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3
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2K
sandeepv
S
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ghdl problem
  • David Ashley
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3
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2K
David Ashley
D
T
modelsim, v93, write to file
  • tami
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3
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3K
Mike Treseler
M
D
Hardware book like "Code Complete"?
  • Davy
2 3 4
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73
Views
4K
Tom Lucas
T
A
Timing Simulation - (ModelSim)
  • Abs
Replies
0
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1K
Abs
A
N
Free Verilog Simulator
  • ngsayjoe
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2
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7K
ngsayjoe
N
W
How to get lowest price for a ModelSim license?
  • Weng Tianxiang
2
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21
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32K
ngsayjoe
N
M
another newbee question
  • martstev
Replies
3
Views
977
Peter
P
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[SystemC] AMBA AHB Bus implementation
  • Herwig Dietl
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1
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3K
deshmukhur
D
S
multiplier
  • Scofield
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1
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1K
Jerrie85
J
L
inc2modL architecture
  • Loppy
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1
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783
Loppy
L
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GHDL 0.25 is released
  • Tristan Gingold
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1
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1K
Pinhas
P
J
assign statement verilog
  • Jerrie85
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0
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1K
Jerrie85
J
A
false edge detection
  • apurva
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1
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1K
Jerry Avins
J
A
Design Of FIFO
  • athulyapg
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0
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981
athulyapg
A
A
Design of Usart(synchronous) in Vhdl using Quartus
  • athulyapg
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0
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3K
athulyapg
A
M
generics in type definition?
  • MM
Replies
3
Views
896
Charles, NG
C
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Compiler can't detect std_logic_1164 package
  • aijazbaig1
Replies
15
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2K
Mike Treseler
M
A
Synthesis for 22v10
  • a
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6
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4K
ghelbig
G
I
Call for Papers - IEEE ISQED07
  • ISQED
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0
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1K
ISQED
I
D
Syntax question
  • David Ashley
Replies
2
Views
1K
David Ashley
D
N
cosine calcs
  • Niv
Replies
9
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3K
Jonathan Bromley
J
A
comparing frequency of two clocks
  • arant
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5
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3K
Thomas Stanka
T
M
clock divider by 2
  • martstev
Replies
3
Views
17K
arant
A
A
Reset asynchronous assertion synchronous deassertion
  • arant
Replies
1
Views
4K
KJ
K
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Arbiter schemes?
  • Davy
Replies
3
Views
3K
Mike Treseler
M
R
Keyboard input help
  • Rishi Dhupar
Replies
2
Views
1K
backhus
B

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