VHDL

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comp.lang.vhdl
B
signal to a generic?
  • blitzgeist
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0
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708
blitzgeist
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R
Configuration for mixed mode vhdl / Verilog
  • Rakesh YC
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2
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7K
smoses
S
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How to open a document whose name is generated based on the current date and time
  • Weng Tianxiang
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7
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994
Weng Tianxiang
W
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Simplex in VHDL/FPGA
  • Mounard le Fougueux
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0
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1K
Mounard le Fougueux
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PLEASE I NEED THE VHDL CODE FOR JK FLIPFLOP
  • hyeazu
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9
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9K
Michael Jørgensen
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VHDL and .txt
  • strykaar
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1
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2K
Adrian Jongenelen
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Teaching VHDL
  • Adrian Jongenelen
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0
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1K
Adrian Jongenelen
A
A
This question seems simpler than it actually is...
  • arubin
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8
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922
jacko
J
K
Frequency Divider Simulation problem using ModelSIM
  • Kyle H.
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3
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5K
Kyle H.
K
C
THE BEHAVIOR CODE FOR 24-BITUP/DOWN COUNTER WITH PARALLEL LOAD AND ASYNCHRONOUS RESET
  • coldplay112
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2
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1K
rickman
R
M
help for a beginner
  • mike-t
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5
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760
Paul Uiterlinden
P
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VHDL language question regarding placement of attributes
  • KJ
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2
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3K
Brian Drummond
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J
Missing direction on entity port
  • jtw
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1
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939
Paul Uiterlinden
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Using a global clock as an enable for flip-flops and RAMs?
  • mav1101
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1
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1K
Dave Dean
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G
Division with ieee.numeric_std
  • Gabriel Schuster
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5
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7K
Nicolas Matringe
N
C
plz clarify this doubt in vhdl
  • chaitanyakurmala
Replies
1
Views
892
Jonathan Bromley
J
C
model sim error plz clarify
  • chaitanyakurmala
Replies
1
Views
1K
KJ
K
C
doubt in process statement of vhdl
  • chaitanyakurmala
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3
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1K
alessandro basili
A
A
VHDL oddity
  • Alex
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5
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910
David Ashley
D
A
fixed pattern generator
  • alessandro basili
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9
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1K
David Ashley
D
C
to alessandro basili
  • chaitanyakurmala
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0
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725
chaitanyakurmala
C
C
doubt on VHDL process
  • chaitanyakurmala
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2
Views
991
Hubble
H
C
doubt in this program plz tell why this error is coming and what modifications i have to do
  • chaitanyakurmala
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1
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1K
alessandro basili
A
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Introducing myself and my project
  • Pete Bleackley
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3
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1K
rickman
R
R
locally static expression
  • rickman
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8
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3K
rickman
R
A
problem in procedure
  • ashu
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6
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1K
Paul Uiterlinden
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B
Vhdl Ram
  • bmartiniello
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0
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2K
bmartiniello
B
V
Error in variable assignment
  • veenamgp
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0
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805
veenamgp
V
M
another counter question
  • martstev
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11
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1K
KJ
K
A
Xilinx BlockRam: VHDL Model
  • Avion
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2
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2K
Avion
A
M
improving code
  • mysticlol
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13
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1K
mysticlol
M
D
A general rule for State Machines?
  • Dave Dean
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4
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1K
Andy Peters
A
E
How to exchange a string between a
  • Eric
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6
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1K
Duane Clark
D
S
Simple design with MICROBLAZE in Virtex 4
  • saurinjpatel
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0
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1K
saurinjpatel
S
W
opening an image, using it for simulation stimulus
  • wallge
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3
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2K
Martin Thompson
M
L
Mixed HDL Simulation-Query
  • Lesalesa
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0
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940
Lesalesa
L
H
pipeline machine construction set
  • homoalteraiensis
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2
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875
homoalteraiensis
H
A
inout
  • Attila Csosz
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3
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1K
Paul Uiterlinden
P
A
Resolving record with enumerated type
  • Analog_Guy
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3
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1K
Paul Uiterlinden
P
T
Loop inside case?
  • Travis
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8
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6K
Paul Uiterlinden
P
U
microblaze lwip
  • u_stadler
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0
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3K
u_stadler
U
N
SPI confusion
  • Niv
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5
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1K
Dal
D
C
doubt about packages in vhdl
  • chaitanyakurmala
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3
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1K
J.Ram
J
S
mac design in vhdl
  • sksaras
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6
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11K
james
J
M
vhdl 101
  • martstev
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4
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3K
willie
W
C
to J.ram
  • chaitanyakurmala
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0
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810
chaitanyakurmala
C
C
how to proceed to know the value of power consumption for our design in vhdl
  • chaitanyakurmala
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0
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1K
chaitanyakurmala
C
W
Calling a JK flipflop through a procedure
  • willie
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0
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1K
willie
W
P
Generic package
  • patrick.melet
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4
Views
3K
David Bishop
D
A
regarding tla2vcd conversion
  • Aravinda.rsm
Replies
1
Views
743
bybell
B

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