VHDL

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comp.lang.vhdl
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need help with sll shifter
  • ohaqqi
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1
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4K
ohaqqi
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FINAL YEAR PROJECT
  • UETIAN
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0
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957
UETIAN
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adding 32bit numbers in 16bit processor
  • isnullpr
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7
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2K
IsNull
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Infering a sequential in RTL
  • rohit.nadig
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4
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1K
Andy
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frequency divider by 2,3
  • JenniferLin801
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0
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9K
JenniferLin801
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timeout in a procedure
  • alessandro basili
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17
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4K
Jonathan Bromley
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VHDL codes for 8-bits convert to 2 bcd
  • aviro25
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0
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4K
aviro25
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A
global signal
  • alessandro basili
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2
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1K
Daniel Kho
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VHDL Standards Overview of Accellera VHDL 2006 Standard 3.0
  • Jim Lewis
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0
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2K
Jim Lewis
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ethernet controller
  • a-bike
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1
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2K
Paul Uiterlinden
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Might be just a bit of topic...
  • Rick North
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1
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804
Rick North
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XdmHelpers:662 ; Timing Spec. warning during map
  • vu_5421
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0
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2K
vu_5421
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Glitches in post-layout (PAR) simulation
  • Manny
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1
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957
Zara
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Modelsim Post-synthesis
  • DualCore
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0
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936
DualCore
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Something stupid with a "case"
  • Pleg
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10
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1K
Pleg
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S
implmenting digital backend of RFID tag
  • shakeelsultan
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1
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1K
Daniel Kho
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Generics vs Constants - what criteria do you use to choose between these?
  • Andrew FPGA
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19
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2K
Jim Lewis
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Instatiating Xilinx RAMs without using core generator wrappers
  • Frank A. Kingswood
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2
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2K
manu
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Question regarding borrow out bit in a subtractor
  • Rishi Dhupar
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4
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1K
rickman
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H
Help me on learning e language
  • hitsx
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1
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1K
Hans
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Port Map Trouble
  • nfirtaps
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2
Views
756
anupam.jain21
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L
About counter in VHDL
  • laura_pretty05
Replies
6
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13K
nysopramo
N
N
Unconstrained array and range direction
  • Nicolas Matringe
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12
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2K
Andy
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B
Help Needed For Asynchornous Transmitter Design Using Vhdl
  • BALAS009
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0
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1K
BALAS009
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VHDL count error when cascading
  • rob
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1
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1K
Mike Treseler
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Inexplicable compilation error
  • better_cs_now
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2
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1K
Andy
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H
implementing switch in fpga
  • hema
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1
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825
Mike Treseler
M
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switch controller design
  • hema
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8
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955
Mike Treseler
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switch design on fpga
  • hema
Replies
1
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770
KJ
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Opencores Problems
  • Pete Bleackley
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2
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880
pbdelete
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need help cascading 3 decoders/counters. weird count sequence
  • k2in5
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0
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1K
k2in5
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C
vhdl ebook.
  • Chris sun
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4
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6K
coolguy26586
C
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Looking for HDL code for sin( a ) and x ** y Functions
  • Derek Simmons
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13
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7K
ditsdad
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M
outputs are in conflict most of the time
  • Martijn van Pottelberghe
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8
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1K
KJ
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G
free vhdl simulator
  • GlobeTrade
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4
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2K
Ed Coombs
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Urgent
  • Mary
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1
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963
Mike Treseler
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M
Need Help for Qaurtus tool
  • Mary
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5
Views
857
Mike Treseler
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C
doubt in variable passing in multiple process
  • chaitanyakurmala
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4
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909
Mike Treseler
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what is the problem with latch inference?
  • VHDL Guy
Replies
9
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14K
fp
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Entity Output
  • Simon
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3
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760
Mike Treseler
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Z
how to speed up XST
  • zty
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0
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1K
zty
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Please help me in registerfile vhdl program
  • madboy
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0
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945
madboy
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Unsigned multiplier
  • Ndf
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1
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2K
Ralf Hildebrandt
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Iterating through a STD_LOGIC_VECTOR
  • funktion
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0
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1K
funktion
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Generate with 2-Dimensional array
  • Ved
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8
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7K
Ved
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M
Ginerics mixed with if elsif else
  • michaelb
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0
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1K
michaelb
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A
verilog tutorial with great examples
  • am_y
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0
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1K
am_y
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J
what happened to opencores.org
  • James Dalton
Replies
8
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3K
am_y
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SCSI
  • Guillaume Zin
Replies
1
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1K
pbdelete
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P
hard to make it generic
  • Pasacco
Replies
3
Views
904
KJ
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